04-01-2010 09:11 AM
04-02-2010 10:13 AM
Have you tried adding shut-down code to the end of your VI that manually sets all DIO channels low? When you stop a VI the DIO should stay at the state in which the VI ends. How are you stopping the VI? Do you just have a stop button the ends a loop or are you force aborting it? Also are you stopping the host VI or the FPGA VI?
PS. Duplicate post here