labview 2010 FPGA: problem with mean-variance subvi

[dan_u]

Ah I see. Thanks.

[JLewis]

Hi Andrea,

1) Unfortunately, the root problem is that the algorithm is very sensitive to quantizations in the data path and the fix relies on computing the extra bits. A single DSP48 supports up to a 18x25 multiply, and the new version changes from a 16x16 to a 20x20. Sometimes the Xilinx synthesis tools will implement a couple extra bits for you in fabric logic, but apparently not in this case. I tried reducing the precision on the square operation to 18x20, but this has a significant impact on accuracy--you may be able to get away with this, depending on your requirements.

A more accurate and potentially cheaper method of doing the computation would be to compute the mean first and subtract it from the data before doing a sum of squares to compute the variance. The node isn't implemented that way because it would require 2 passes through the data, storing each frame until the mean computation is complete. This might be an option for you if you don't care about latency (the DC-RMS node provides the Mean Square and RMS computations you would need to build something like that).

2) For non-power-of 2 sizes, you would need to replace the casts with multiplications by a 1/N precomputed constant, or you could use a divide if you want it to be run-time configurable or to save multiplies. You can configure a node for a non-power-of 2 size and choose "Convert to SubVI" from the pop-up menu to see an example of code that does this (it suffers from the same overflow issue, though). Be aware that this is significantly more expensive in terms of multiplier usage (Xilinx may use either DSP48s or logic to make constant multiplies).

[JLewis]

Dan, I forgot that fixed-point casting can also be done with the Reinterpret Number node available on the Numeric>>Fixed-Point palette when under an FPGA target.

[dan_u]

Thanks for the info. I sometimes used number to boolean array and boolean array to number, which should be the same as FXP to INT and INT to FXP. There is a small difference, though: a INT can only be 8,16,32,64 bits, while the boolean array can have any size.

I don't know how the compiler will handle that, but to losslessly divide a 20bit FXP number you'd need a I32 (adding 12 bits) or a boolean array of size 20 (no change in size, so this should be a free operation on the FPGA).

[JLewis]

That's a good point. Since the bits are being created and trimmed before any registers are involved, I was counting on them being free. Both the Boolean array and Reinterpret options are more explicit, though, so probably better choices.

Note also that you may see some awkward-looking constructions in the code underneath these Analysis nodes because they are scripted from templates. Not every configuration comes out looking like what you would create by hand. We do attempt to ensure that they compile to the same or very similar hardware, though.

[ron3721]

Hi Jim,

I had the same problem as Andrea: I'm trying to aquire data (I16) continuously on a PXI-7833R fpga board and calculation the variance of each 1000 samples (this number can also vary). The express VI never behaves as expected.

I checked your solution VI, tried to calculate the variance of 1024 data point (as required to be 2^n), and for that I also changed the "count -1" value to 1023. But it does not seem to work. I don't know if I did it in a right way. So could you have a look at the code (saved in LabVIEW 2011)?

By the way, I also included the original (old) express VI in the code, and changed the sample number to 1024, and it did not work. I'm wondering probably I did it in a wrong way, because if there is a problem with this vi, it should not be included in the packet, right?

Thanks in advance!   &    looking forward to your reply

Ron

[JLewis]

Hi Ron,

It's a bit more complicated than just changing the "count-1" constant. You need to visit each of the orange-labelled nodes or constants and analyze what the type needs to be for the given configuration. Changing the number of samples affects the accumulator widths needed to prevent overflow, and the type of cast needed to implement the power-of-2 divide. Setting all those values correctly is what the Express VI takes care of for you.

I've made the adjustments in the attached VI. Let me know if you have any questions about the changes.

Jim