labview fpga not compatible with std_logic_vector type vhdl ip

[ghattas.akkad]

hello

i am having a problem connecting an 8 bits integer to  a 8 bits std_logic_vector

the vhdl ip in the labview fpga is being handled as a data type of fxp (fixed point)

how can i make the connection so that the inputed data doesnt change while casted (i want to input a 8bit unsigned value to the data_ina std_logic_vectore type)

thank you

[ValkoA]

Dear ghattas.akkad,

Is there an error you're experiencing with your application, or is the datatype mismatch simply unsightly? 

The std_logic_vector type is stored as FXP because it is of variable length (so you can create any vector length, not just 8, 16 or 32 bit). If you have a <+,8,0> FXP, that is effectively an U8 (different type, but it is the same data inside), and will be interpreted as such, even if it is not the same type and is being coerced. So, if you have your logic vector interpreted as <+,8,0>, you can just ignore the coercion dots on the inputs and outputs. The FPGA translator will ignore them for sure, because there is no logic involved.

If your vector FXP is configured differently, you may have to convert your data. Do his with the Numeric conversion palette.

Kind regards:

Andrew Valko

NI Hungary

[ghattas.akkad]

the problem is that i am inputting a constant 10 from the fifo everytime but the output from the fpga side is going up  to 4000 and 3000

the vhdl ip simply shifts the data always the way from in to out

[T-REX$]

I'm not entirely sure that the data-type is the issue, but if you look on page 4 of the CLIP configuration page, you can change the LabVIEW data type of your CLIP node to a u8 (as long as it's 8bits wide).

I'd probably have to look at the project (full code, HDL included) to figure out the issue if this isn't it.