Hi guys, 😄
I use the sbRIO9651 for Testing a Prototype. I use the CFG File (DevKit of the Evalboard) to create some Signals to write them to PMODx
In any case even i just write constant true/false to the PMOD Wire (PMODx_pinx_out) combined with preconfigured PMODx_pinx_enable = true, i receive a Timing Violation.
I can write to one PMOD Signal without an error - writing to two Pins of the PMOD i get the following Timing Error: (see Attachment)
In other VIs i got also this timing violation.
I was searching for this Problem in forum, but i couldnt find a solution.
- Hybrid Mode is not available for sbRIO9651
- "Using multiples of the same I/O node leads to timing issues"
I just write once to the IOs
- The Problem is also at other VIs, so it makes no sense to add my VI - is by the way always the same Signals with the Timing error
- The Timing violation is 8 ns( = 125Mhz) missing 0.02ns -> My VI doesnt need this Speed
I tried at my VI to reduce to 1 MHz at SCL
I tried to pipelineing
- The Problem is at "EMIOENET1GMIITXD" and "ENET1_GMII_TXD"
which is Ethernet. I didnt activate it at FPGA.
I just found in CFG that ETH2 cant be enabled. So its in use, but i guess because of the RT Linux on ARM Core of Zynq
So why has Xilinx Compiler a Problem with the ENET1 GMII TXD ?
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the VI_example.png is the last version without any logic anymore. - Still there is the same Timing Error.
Why cant i write onto the PMODx ?
Thanks for help!
best regards
Florian
