problem with timing in cRio and FPGA

[Joaopsoliveira]

Hi,

I'm developing a programm to measure the position of a device using some quadrature encoders.

What I'm doing is using the FPGA interface to aquire the position and then usign the Real-Time send the number of the counter to a host pc to create a data file. In the RT environment  I create an array with the position and the time that is aquired and using shared variables I send the array to the host PC.

But I've got some problem with the timing. The sampling time is unstable, I'm using a timed loop to control the sampling but after some acquirements, the period of the data sampling starts to increase, as you can see in the Attachment image file. In the image attached, I used a period of 250us and after some acquirement the time gets twice and 3 times longer before I clean the array and start to create a new array, when the period start in 250us again. so the problem is that I should get a period stable in 250us instead of this steps of increasing period

[Gak · Accepted solution]

Are you using Build array to add new data points? I will suggest to use "Initialize array" function and "Replace array element". It will reduce time it takes as compared with build array.

I can not open your code as I have LabVIEW 2010.

[Joaopsoliveira]

I changed the program replacing the Build Arrays funciton and now it's working fine

Thank you for your help!!

[Suse]

Hi,

I could see the code and can approve the previous post.

It's important to make a initialization of the array first with defined size. Then you can take the function replace array subset to fill the array with new values. With this method, the timing is much better and you don't run into memory troubles on the FPGA (see attached VI).

Here some Benchmarks:

LabVIEW FPGA Benchmarks for Virtex-5 R Series Targets: http://zone.ni.com/devzone/cda/tut/p/id/7242

You find some simple benchmark structure attached to find out the performance of some code. One additional information for benchmarking: don’t make a benchmark by placing a while loop around all timed loops on RT or all single cycle timed loops (SCTL) on FPGA because you disrupt the parallelism.

I hope this helps you.

Best regards

Suse

[Joaopsoliveira]

What I did is pretty much the same of the preallocate method of the VI attached. Creating huge arrays with 300,000 elements I got a very significant  improvement in the timing, and the whole program is working faster than expected.

Best Regards.

Joao