project and FPGA v odd behaviour

[Dan_Acres]

I've been having an odd issue with my main project and the FPGA VIs inside it.

It appears that a recent revision/replacement of some of the code (replaced subVIs with newer revisions with different names) has prompted the VI to load unused VIs when I save it.

The story becomes stranger because I can create a completely blank FPGA VI within the project and it still loads the same SubVIs when I save it.

I can repeatly save the VI and the same (now non existant) subVIs will be loaded each time before saving can complete

The SubVIs do not show up in the VI hierarchy and are no longer in the project at all - but are still loaded by a VI that bears no resemblance or relation to the original VI.

Is my project completely broken?

If so is there any way to fix it without starting from scratch ?

Thanks for any help in advance

Dan 

[Dragis · Accepted solution]

do you have any vis under the fpga target that might still reference the missing subvis? if the project thinks you still have a dependency on those missing subvis they will show up (with a warning i believe) under the 'dependencies' item of the fpga target. when you save a vi in the fpga context, labview loads the other vis under the same target to ensure they are still valid and to update some book-keeping information. if you have any other vis that are still broken on disk (even if they get fixed up on load), you'll have to wait for them to load each time you save the vi in question.

[Dan_Acres]

That makes sense - I tried deleting all the other 'top level' VIs from the project and it stopped complaining/loading during saves.

Odd I haven't noticed this behaviour before though as I've done this all 50 times before... 

Thanks for the help

Dan