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reset counter from Host?

Hallo,

 

I had a Problem with the reset of my counter. I use the Card 7833R ( PCI ). How can I reset my counter from the host? If I send a true ( constant ) it ist always reset, and it should only reset on especially events.

 

Thank You!

 

Martin 

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Hi Martin,

you can use edge detection. Store the old "reset" value in a shift register. Use a greater function, connect the reset button at the top connector and the value from the shift register at the bottom connector. If the result is true, reset your counter.

 

Mike

Message Edited by MikeS81 on 02-16-2009 09:54 AM
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Hallo Mike,

 

I couldn't understand your idear. Can you send me a little screehot?

 

Martin

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This is what Mike says
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Hi krunal.ele,

thanks for the example, but you should store only the reset button value in the shift register, not the result of the greater function.

If you store the result of the greater function and the reset button is very long true, then the result of the greater function will toggle from iteration to iteration.

 

Mike

Message Edited by MikeS81 on 02-16-2009 10:41 AM
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Hi Mike,

 

thank you. It doesen't work how I need it. I send now the part from the hostVi which should reset the counter, but it doesen't work. I send two bursts to an IR-Receiver a strong Burst and afrer it a weak burst to test IR-Receiver from vishay. Between the two burst I change the repetiontime ( trep ) and always after 25ms trep or two pulses on the output of the Receiver  the counter must reset. After Reset It change values for the new meassurement

 

Thanks

 

Martin 

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Hi,

 

the VI-part.

 

Martin

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Hi Martin,

where do you have problems, in sending the reset value to the FPGA?

 

Mike

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Hi Mike,

 

the problem is, that the counter rest to fast. There aren't two pulses on the output from the receiver and the counter resets. It resets correct after 25 ms but not if two pulses on output received. It resets the counter yet one burst is received.

 

Martin

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Hi Martin,

did you check if you really receive two pulses? Can you show the fpga vi?

 

Mike

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