resetting compactrio programmatically

[suni]

I am using Compactrio 9014 with FPGA. Is there a way to reset the compactrio programmatically (hardware reset)?Thanks!

[MikeS81]

Hi suni,

see this and this link, please.

Mike

[suni]

Hi Mike,

Thanks for the reply.

If I reset the cRIO using the method in the link that you pointed does that resets the cRIO and start running the RT code automatically?

[Burt_S]

Hi Suni,

The RT VI will only run on reset if it is set to do so.  You can find more information about configuring startup VIs on RT targets here.

[Burt_S]

Sorry for the bad link.  Lets try this.

[suni]

Hi Burt

Thanks for your reply.

I want to reset RT target (code in the RT) and fpga vi and restart both RT vi and fpga vi. While RT target and FPGA vi is rebooting I don't need control application to run. My primary purpose right now is to reset RT target (hardware and software) and fpga vi using a control(button) in the RT vi. As soon as i hit this reset button before it actually resets the RT VI and FPGA VI, I want to write value of zero to all analog output modules and false for all the digital I/O modules and then reset the RT vi and FPGA VI. Then i want to restart both RT and FPGA automatically and display  a message saying system is ready again in RT vi. I was trying to use system reset I/O in FPGA to reset the RT controller. I need to set this to false after i set it to ture to preventresetting of RT again. Can i do this right after i set it to true?   could you show me a direction i can start this?

[Burt_S]

Hello Suni,

As far as I know, you can set the I/O line to false immediately after setting it to true and the controller will be reset.  If this does not work, you can always add a little wait to give the controller more time, but my guess is that this should not be necessary.  Also, once the RT resets, it will not automatically reset the FPGA code.  What you can do instead is put the entire FPGA code in a loop and have it wait at the beginning of the loop for a signal that the RT has finished rebooting.  Once this signal is received the FPGA code can continue to run like normal.

An easier way to do this would be to reset the controller in the RT code using the Reboot Controller VI.  This would give you more control over when the controller is reset and would allow you to more easily reset the FPGA code.  Unfortunately there may be an issue with using this VI with the cRIO that you are using according to the information here, which is why I am suggesting this alternate method.  Hope this helps!

[suni]

Hi Burt,

Thanks very much for your reply. That was very helpful.

The alternate method you are suggesting is to use to fpga system reset I/O line right. If i use that to reboot the RT controller, how do i send a signal to the FPGA vi that RT is finished rebooting. Like you mentioned I would like to avoid using reboot controller vi. Thanks.

[Burt_S]

There are likely many ways to do this.  Perhaps the easiest way would be to use the Read/Write control to set a boolean indicator in the FPGA VI to true at the beginning of your RT code.  As soon as this boolean gets set, the FPGA code will know that the RT is up and running again.  Just make sure to set this back to false on the FPGA before you reset the controller.  Hope this helps!

[suni]

Hi Burt,

Thanks for the reply.

Is there a way i can reset both RT and FPGA at the same time and restart bothe RT and FPGA vis?. While FPGA resets I want to write default values to all the ouput modules in the chassi. Thanks.