rt

[Harss]

Hi,

In my application I am transferring sample values of signed fixed point 24,5 data type and the timestamps of unsigned 64 . Since the acquisition is at 1 MS/sec I am using FPGA to RT DMA FIFO for data transfer. Since, the FPGA to RT DMA Fifo does not support clusters hence, I am using two seperate DMA FIFO's for transferring sample and the timestamp values onto the RT . Could you please suggest any mechanism by which I can synchronize the FIFO Read on the RT so that I get each timestamp value against the sample value?

Thanks.

[thunderstorm]

Hi,

You could send your fixed point data as u32, split u64 into two u32 and create an array.

In this case, you will know that each three consecutive elements represent one block of data, you will re-do your data back on RT.

Make sure that you read on RT n*3 number of elements and just decimate by 3.

Cheers,

Thunderstorm

[Harss]

Hi,

Thanks a lot for your prompt response . In case I convert the signed (24,5) fixed poit into unsigned 32 I tend to loose the precision Eg:0.15443 gets represented  as 0 . Further conversion back into signed fixed point on the RT fails to provide the same precision.Also there seems to be an issue dealing with negative numbers.

Could you please suggest?

Thanks.

[Harss]

Hi,

I just happened to check this link.

https://www.ni.com/en/support/documentation/supplemental/21/fixed-point-fxp-to-single-sgl-conversion...

With this link it seems possible to be able to maintain the precision of fixed point by storing the signed fixed point value as unsigned 32 on the FPGA .

I guess this wont affect the sampling rate because the sampling requirement is 1 MS/sec.

I just wanted to know how to split unsigned 64 into two unsigned 32 bit values I will try this and get back to you asap.

Once again thanks for the help .

Thanks.

[Sam_Sharp]

There is a split numbers VI in the numeric data manipulation palette which splits a number in half and returns the upper / lower significant part (e.g. splits a 16-bit integer into two bytes etc.).

[Harss]

Hi,

Thanks a lot for your input . This really helped me I am now able to split unsigned 64 bit into two unsigned 32 bits on the FPGA using split number function and the merge number helps me to reconstruct it back to unsigned 64 bits on the RT.

🙂

I just had a one last question:

Could you please suggest the configuration for the local FIFO which would be used  to transfer timestamps onto the FPGA to RT DMA Fifo . I guess unsigned 64 with number of elements set to 1 would be okay. Could you please suggest?