pls if someone who met the issus same as the annex:
We use Labview2022Q3+ FPGA+ RT environment, and when we edit to download the code to sbRIO, the unique error happened to show: Timing error. (After a long 10min+ downloading)
at last it prompt :
设计需要该非程序框图组件。内部名称：/CrioCartContResource1/CartridgeControllerCorex/IroncladSideband.CrioPassthroughSidebandEnginex/CrioSidebandEngineCorex/CrioSbSerialReceiverx/CrioSbDataCaptureDataPathx/sDataFall_reg[0]。
(design need additional coms? )
设计需要该非程序框图组件。内部名称：/Bit0Flop_i_1__0/O
设计需要该非程序框图组件。内部名称：/CrioCartContResource1/CartridgeControllerCorex/IroncladSideband.CrioPassthroughSidebandEnginex/CrioSidebandEngineCorex/CrioSbSerialReceiverx/CrioSbDataCaptureDataPathx/Bit0Flop/GenClr.ClearFDCPEx。”
we no sure what it is? if we lack sth COMs or there are more specials? The basic VI to execute is only a “while” loop and "timer"
So if anyone who knows pls takes your advice. Thanks a lot and wishes
...Regards
