single FIFO DMA reading from two analog channels

[GrantS]

Hi,

    I have a question on a method of transferring data from two analog inputs to a single FIFO DMA in FPGA. The code is outlined here: http://decibel.ni.com/content/docs/DOC-6303. If I'm using this method, and I output to a graph in my host VI, will the timing in the graph reflect the same timing as the signals that were input? Or will their be phase lag between the two signals?

Thanks,

    Grant

[charris · Accepted solution]

Grant:

Since there isn't any timing information carried with the signals in the FIFO, there won't be any phase lag on the chart.

Hope that helps. Let me know if I left something out or didn't explain that very well.

Thanks!

[GrantS]

Thanks for answering my question Caleb, you explained it pretty well.