timing violation Labview FPGA

[AFLAMENT]

Hi,

I sorry i newbee and i must developt an aquisition systeme quickly,

I not understand why my application is a time violation?

Someone to help me?

[P@Anand]

What do you mean timing violation? Are you getting the error message while compilation? Can you please show the complete error message?

[AFLAMENT]

HI,

Hoops i no save the compilation report file 

This message appear at the end of compilation process.

[P@Anand]

I believe you will have the compilation log saved inside the FPGA directory in C Drive. You can once again perform comiplation and check what happens.

[AFLAMENT]

sure, i lunch compilation, 25min later I must leave office and now I did not have access to computer..

[AFLAMENT]

If you look at the joined screen copy of my VI, can you see something of wrong?

[P@Anand]

I am really unclear with the functions since I don't have FPGA toolkit in my personal Laptop, but it seems Ok. Why did you add "Stop" to Stop the acquisition for the module? Also keep the start before the while loop and wire the boolean to it, to make sure that the "Start" executes before the loop starts.

[crossrulz]

I'm guessing that WHILE loop is supposed Timed Loop.  That way the loop will execute in a single clock cycle.  But I somehow doubt you want it to update that quickly.

How fast are you trying to take these samples and pass them on to your RT?  What device is this FPGA going on?

[AFLAMENT]

Did I must use start in first to start module?

When VI is start, did loop never stop if I link F to stop loop?

[AFLAMENT]

He sorry for my bad english,

Max time sample and pass to RT is 10 ms, FPGA is a Xilinx of a module c-rio