where to find FPGA trim report of the compiler

[Ex-NISH2]

I have problem when compiling my FPGA VI for cRIO 9101.

It seems that some of my signal is trimmed, but I can not find the trim report. 

Also, I don't know what kind of problem in VI may generate this issue.  My original VI was OK under LV 8.0 (FPGA).  But I got Slices overloading (108%) under LV 8.20.  After changing several front panel clusters into constant values, I reduced the slices to 90%, and nothing else is used more than 80%.  However is still have this problem.

The error message is here:

++++++++++++++++++++++++++++

Using target part "2v1000fg456-4".

Mapping design into LUTs...

ERROR:MapLib:661 - LUT3 symbol

   "mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n00051" (output

   signal=mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n0005) has input

   signal "mytop/n_898/resVI/n_676/n_673/n_662/n_651/eo00000cbc" which will be

   trimmed. See the trim report for details about why the input signal will

   become undriven.

ERROR:MapLib:661 - LUT3 symbol

   "mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n00051" (output

   signal=mytop/n_898/resVI/n_676/n_673/n_662/n_651/n_645/_n0005) has input

   signal "mytop/n_898/resVI/n_676/n_673/n_662/n_651/eo00000ba0" which will be

   trimmed. See the trim report for details about why the input signal will

   become undriven.

Error found in mapping process, exiting...

+++++++++++++++++++++++++++++++++++++++++

[YuYiming]

Source code with the trim errors during compilation for PID Demo in LabVIEW 8.2

[jdigiova]

Actually it appears that the code you have didn't mutate to 8.20 correctly.  I looked at it and when you try and open the properties of the saturation VIs in the Tach subVI it cannot fidn the property page.  This tells me that the VI is no longer working properly.  If you look at the compile report just above the Error messages you see some warnings about a prim_unknown.   This is do to a floating point number being on the diagram.

Was this VI ever opened and saved in 8.2 without LabVIEW FPGA installed?  Can you provide me the 8.0 version of your code so I can make sure it mutates to 8.20 okay? To fix the issue you should open the 8.0 VI again in 8.2 (with FPGA installed) and then save it in 8.20.  It is important to only save VIs in the latest version if all the modules they need are installed.

Regards,

Joseph DiGiovanni

[Ex-NISH2]

Exactly, I had some problem with my LV FPGA, and asked some one else to save that tach.vi to 8.2 for me.  It seams that he has no LV FPGA installed.  An interesting thing is that LV didn't give me error when I open the tach VI.  If I have RT VIs, such as RT LED control opened on 'My Computer' or  windows VIs, such as menu bar control VI opened on RT,  I will get broken wire.  Is it possible to have such a check for FPGA?

Hui

[jdigiova]

For the most part you will get a broken arrow when you have unsupported datatypes in FPGA.  The saturation functions are an exception.  In general, when things are correctly installed the saturation VI is really just a placeholder for the FPGA code that will need to be created for it.  However, you can run the VI in emulation mode and therefore we need to define the behavior of the code for emulation mode.  This behavioral code is what uses floating point numbers that you see on the block diagram of the function.  We do not check for unsupported types in NI functions, because we expect them for emulation.  When emulation is off and you run the VI we see that the saturation function is there and generate special functional code.  However, if the VI is saved in a version without FPGA this flag is removed and we no longer generate special code for the function, but rather just generate code for the diagram the way it is (floating point and all).  I have filed a CAR to the developers in order for them to catch this error earlier in the process and provide a cleaner error message.

Regards,

Joseph D.

National Instruments

[Ex-NISH2]

Cool.  Thank you so much.