why I cannot get the expected timing from FPGA VI?

[auree123]

Hi,

Can anybody help me in finding out the reason, why I am unable to get the data from FPGA in my desired sampling rate.

I gave loop rate as 833 usec in FPGA side (that is 1200 sam/sec).

I applied time out as 5 ms and set 1200 elements per loop iteration in Read Fifo at real time side.

When I tested the FPGA VI in the developement computer, it runs really fast, but, if I run this with cRIO, it becomes way slower than the desired data rate ( 833 usec in this case).

Any feedback would be appreciated.

Thank You.

[PaulRB]

Hi,

I have a few comments. First, in the FPGA VI, make sure that the loop timer is the first thing you are setting in the while loop. To do this, place the loop timer in the first frame of a sequence structure and everything else should go in the second frame.

On the RT VI, since you have the while loop set to run every 5 seconds, and you're only reading 200 of the 1200 data points every iteration, it is not surprising that you are seeing poor performance. I would expect your FIFO to overflow fairly quickly. 

What I would do is remove the IRQs from the FPGA and RT since they aren't serving a purpose. You might want to model your FPGA VI off of the example Basic DMA - cRIO.lvproj, which can be found in the LabVIEW example finder.

Post back with any troubles you have.

Thanks,