1422 documentation

[caribou]

Hi  I am trying to resurrect a custom single x-ray photon counting camera system that has a 1422 frame grabber...

Yes I know it is no longer the state-of-the-art. I cannot upgrade as  there is no funding to buy new hardware.

I cannot find documentation---many of the links that reference it are "dead" eg in this thread:

https://forums.ni.com/t5/Machine-Vision/Enable-lines/m-p/313819/highlight/true?profile.language=en#M...

In that link, I  also found this:  "What are the timing diagram re..."  is a dead link.

I need to know how to set the frame and line synchs on the enable lines.

I remember there were peculiarities in the device needing continuous pixel clocking even when line synch/enable

was inactive and that line synch had to be unselected for three pixel clocks.  This information is  not present on the users manual.

Help!!!

Thanks

[SSPTest]

Hi Caribou,

Thanks for reaching out. It's a cool application you have. I'm not sure how helpful we can be with some of the older cards since a lot of the knowledge has moved on, but maybe we can be of help.

Here are some of the links I found:

Digital Camera Basics

What are the Timing Requirement of a the 1424 and 1422?

IMAQ PCI/PXI 1422 User Manual

Hopefully this helps! Goodluck!

[caribou]

Hi.

Thanks for the response

My issue is that the critical links (like the second one in your list)

are *dead* --- that is they bring me to an inactive page.

How can I find that info??

We need to go back and demonstrate performance of sensor before we have a chance for more

$$---- then we can upgrade to cameralink

[KeddyC]

Hi caribou,

I apologize, the ones in the original post are all broken for me, but the ones I posted, all work on my network and browser. Let me know what one's don't work for you. I uploaded an image of the content of the second link. Hopefully it helps.

[caribou]

Thanks!!

That was the diagram that I remember.

So pixel clock has to be continuous.... but the frame synch only has to go low for approximately

a **time period** equivalent of three lines--even though a continuous hsync is recommended.

I have the system running but it is un reliable and inconsistent---it runs for a while but then loses synch and

gives me a time out error.

-

[KeddyC]

Caribou,

---

So pixel clock has to be continuous.... but the frame synch only has to go low for approximately

a **time period** equivalent of three lines--even though a continuous hsync is recommended.

---

This is correct.

---

I have the system running but it is un reliable and inconsistent---it runs for a while but then loses synch and

gives me a time out error.

---

If you post your code, maybe we can see if it's a software issue. Otherwise make sure all of your cabling is functional.

[caribou]

Well it is not code in so much as it is firmware.  I hope you can understand the following description.

Camera is FPGA based  with a 16bit adc. It operates in vacuum chamber. ---Since LVDS output eats up

pins on our vacuum feed-thru,  we are sending the pixel data to frame grabber as pairs of double bytes.

The pixel clock is being  double tapped so for two pixels it  looks like:       ____--__--___________--__--____

one pixel's byte1 and byte2 in rapid succession then the next pixel's two bytes etc etc.

--this is all happening when line sync is asserted.  We operate frame grabber as if we had a byte camera, and then

recombine bytes into a words  offline.

During the time period that the line sync is not asserted, we send a bunch of regularly spaced pixel clocks.

My gut feeling is that the frame grabber does not like the double taps and would prefer to have everything

more regular.

Let me know what you think

Thanks again for the comments

[KeddyC]

It should be able to accept Double Tapped 16 Bit signals. I don't know if I can comment if the the 1422 prefers just a standard high/low pixel clock, but I'd just recommend that you double check you are operating everything within spec.