05-10-2010 10:15 AM
Solved! Go to Solution.
05-12-2010 10:52 AM
Hi Chris,
I did not find any known issues documented regarding this. A few questions:
1) What driver version are you using?
2) When you mention changing camera modes, are you referring changing the bit allocation configurations or something else?
05-12-2010 12:41 PM
Thankyou for your reply Tejinder G.
I am using NI-IMAQ 4.3
The camera mode change involves downloading a new program to an Altera FPGA. It takes about 0.5 seconds to reprogram and start producing new transmit, line, and frame clocks to the camera link transmitter. During download, the transmit, line, and frame clocks all stop in the low state.
The problem is occurs on all of our CCD camera test systems using the PCIe-1429. It occurs using our software to acquire images and using NI software. On the same cameras we can swap out the camera link connector board and use parallel LVDS with the NI-1424 frame grabber. The NI-1424 always worked correctly.
Thanks,
Chris
05-17-2010 08:02 AM
Do you know if the frame/line clocks complete before the FPGA is reprogrammed? If LVAL or FVAL fell prematurely (before all of the line/frame was received), and the PCIe-1429 only saw a runt frame, I would expect the PCIe-1429 to respond with this timeout error.
Can you control where in the frame the FPGA is reprogrammed (such as programming the camera to only output frames when triggered, and then not sending a trigger for some time before changing modes)?
05-17-2010 09:47 AM
Daniel,
I altered my timing program to listen for a request from the computer and stop all timing only at the end of an image readout and then wait to be reprogrammed. That prevents an interruption in the middle of an image. I still get the timeout errors.
Note that once I get a timeout error they will keep occurring until the cameralink transmit clock is interrupted again. I would hope when issuing a grab command after a timeout, the NI device drivers reset internal line and frame clock counters.
Chris
06-11-2010 12:16 PM
Apparently there is some bug in the DS90CR287 channel link serializer. The phase lock loop sometimes fails to produce an output serial clock to the frame grabber with the proper duty cycle if the input clocks are interrupted. A phase lock loop should be able to recover from that. We noticed National Semiconductor changed their spec sheets to require power cycling the DS90CR287 after any of the input clocks are interrupted. We implemented the power cycle procedure and now the timeout errors appear to have stopped.
All fixed!
06-14-2010 09:02 AM
Chris,
It's good to hear you found a workaround. Thanks for sharing your solution.
-Daniel