Synchronizing Two PCI-1409 boards

[PBatson]

I have two slow scan video signals which are defined by a single set of HSYNCH (200usec) and VSYNCH(200msec) pulses, but which do not have a pixel clock.  I have set up 1409 board number one to generate PCLK(9.73Mhz) in External Lock Mode, strapping PCLKOUT to PCLKIN.  TRIG(0) is strapped to HSYNCH_IN+.  So the 1409 is generating a pixel clock which it then uses as if it were generated by an external camera.  This setup gets me 1024x1024 pixels in 200ms in the 1409 board one.

In order to get the second video signal, I bought a second 1409 board and have used an identical camera file for it.  I have wired it exactly the same as board one, except I do not strap PLCLKOUT to PCLKIN, but instead connect Board two PCLKIN to Board one PCLKOUT.  I thought this would give me synchronized acquisition of the two video signals.

I get, instead,  a DMA time out on board two.  Board one operates ok.

I tried strapping PCLKOUT to PCLKIN on the second board so the boards would work independently.  This works marginally, but I see an apparent horizontal interference pattern in both boards video acquisition which looks like a beat frequency between the two boards' pixel clocks.

What does this sound like to an expert?   Perhaps the pixel clock is garbled on board two by a grounding problem?  Has anyone else tried this kind of set up.  This is a slow scan analog acquisition where no pixel clock exists.  This has to be generated, somehow, in a way compatible with the HSYNCH and VSYNCH signals.

Thanks,

  Phil Batson

[PBatson]

OK, can someone tell me the real characteristics of PCLKOUT?  What is the frequency range and what is the drive capability?  The user manual specification (page A-1) says Internal Pixel clock - 11.6-25MHz.  Measurement and automation explorer (3.1.1.3003) external clock gui allows 0.1-20MHz.  Table 4-1 in the user manual says 500kHz-40MHz.

What is the drive capabilityWhen I strap PCLKOUT to PCLKIN I get a 2.5V pixel signal.  If drive a second PCLKIN line, this drops to 2V  -- very marginal for TTL.  Do I need to buffer PCLKOUT?

Phil Batson

[PBatson]

And is PCLKOUT/IN always differential, sometimes differntial, depending on the Signal Level option in the interface properties, or always TTL? 

[David S.]

Hi Phil -

It looks like you've already discovered to probable causes of your trouble.  According to the NI-1409 User Manual:

• The minimum rated frequency generation for PLKOUT is 11MHz.  You may be able to generate the 9.73MHz signal from there, but I can't guarantee that it will generate a clean, useable pulse train.
• PLKOUT is changed between TTL and RS-422 signals using the Signal Level setting in MAX.
• I can't find a spec on the line driving capability of PCLKOUT, but you may have to buffer the line if you want to drive two boards with it.

Some of the pages you referred to didn't seem to correspond with the latest release (June 03).  Just in case you have an older copy, it can be downloaded here: NI-1409 User Manual

[PBatson]

Thank you.  This helps very much.  I have managed to get my application to work by strapping PCLKOUT/IN together separately on each board.  The pixel clock generation phase locking with HSYNCH seems accurate enough that this generates pixel clocks on each board that are (amazingly) in good registry with each other.

I can live with this unless I see artifacts in my data that are caused by inaccuracies.  Then I may try buffering of one clock for distribution to each board.  In that case I will seek additional advice to be sure I fully understand the board requirements.

Thanks for your help.

Phil Batson