What does Sigle Cycle Timed Loop mean?

[Waran]

Hi,
What does Sigle Cycle Timed Loop architecture mean?If I have a sequence structure in my program does it get completed before 25 ns or the entire program itself gets completed in 25ns?Thanks in advance!

Waran

[bilalD]

Hello

This is the Measurement Studio forum. You will get a better answer if you post to the LabVIEW Targets forum.

Thanks

Bilal Durrani
NI

[pjtanz]

Hi Waran,

The single-cycle timed loop (SCTL) is a special case of the new LabVIEW timed loop structure. It is available in version 7.1 of LabVIEW FPGA ModuleThis loop executes all functions inside it within one 25 nsec �tick� of the 40 MHz global clock.

If you are writing you code to be compiled and run on an NI-RIO target, and if the functions that you use are able to be executed in one tick, all of your code in the loop should be executed in 25ns.

I hope that this helps.

Regards,
P.J.
National Instruments - FPGA Applications Engineer