using NI-9411 in a timed loop clock less than 40Mhz...

[paubine]

Hi,

I'm using a cRIO for motion control. I have a counter that I modified a little bit (from the softmotion examples) and once compiled (unfortunately after 1 hour ...), I have an error saying that I couldn't acheive the desired timed loop clock of 40.4 MHz... the clock rate able to acheived was 40.16 MHz (really near)...

So I had a derived clock of 38.75MHz but this time, before compiling, i have an error saying that theses inputs can't not work at with this time loop clock...

The timed loop counter for this encoder only have to be more than 8000 Hz (1rev/s with 8000 pulses/revolution)

What can I do?

Thank,

Patrick

[paubine]

ok... I removed 2 unimportants indicators and it passed the compilation...

Still interresed if there is solution for next time.

Thanks,

Patrick

[Jochen]

Patrick,

please have a look at this FAQ about the Single Cycle Timed Loop. If provides information about what's working inside a SCTL and what's not working.

Regards,

Jochen

[paubine]

I know that a 9411 device can run in a SCTL at 40Mhz.

What I don't understand is that I can't run the loop below than 40Mhz.

I read in the FAQ that some device can not run above 40Mhz, but in my case, I want to run in slower....

Can it be because I'm asking the same device to run 1 SCTL with DI0, DI1, DI2 at 40Mhz and 1 other SCTL with DI3 DI4 DI5 at a different loop rate.. (38.75MHz) ...

Thanks,

Patrick

[Jochen]

Patrick,

a timed loop on an FPGA target always acts as a SCTL. "Single Cycle" refers to the board's master clock, so that means, that the timing is typically fixed to 40 MHz. If you want to run processes at lower speed, you could use a normal while loop with wait instructions, but this method generates less optimized code.

Jochen

[paubine]

I understand now.

Thanks