11-09-2009 08:55 AM
Hi,
I'm using a cDAQ -9172 system with two types of modules connected,
Mod 1 NI 9215 BNC
Mod 2 NI 9215 BNC
Mod 3 NI 9229 Screw Terminal
Mod 4 NI 9229 Screw Terminal
I am aiming to use this as a simple data logger application to record multiple voltages at the same time. The DAQ is set up to use a 2kHz sample frequency and sample continuously. The measurements from the DAQ are then to be presented graphically on the VI and written to file. Which is all enclosed in a while loop.
However when I apply the same signal to both types of modules (i.e. mod 1 and mod 3) and try to take a reading using the DAQ assistant VI there is a constant 40 cycle seperation between that on the 9215 and the 9229 modules. I have varied the sample frequency 1k - 2k - 3k - 4k and all seem to produce the same 40 cycle seperation. I have also tried to include the "Delay Values" block to remove these cycles - however this seems to use the frequency of the while loop the DAQ is in, rather than the sampling frequency of the DAQ it's self.
And I'm just wondering if anybody has any ideas on:
a) why this is happening and how to fix it.
or
b) a work around which would allow me to shift the data to align it in time.
Cheers,
Mark
11-10-2009 07:49 AM
Hi Holroyd
The 24-bit resolution Analog Input (AI) cDAQ modules use a delta-sigma
converter and an oversample clock to read the analog data. There is an
inherent input delay due to built-in analog and digital filtering. If
the module uses simultaneous sampling, each of the channels on the
24-bit module will be synchronized. However, if you are also reading
from an AI module that has a lower resolution there will be a finite
offset between the 24-bit resolution module and the lower resolution
module.
The delta-sigma input delay can be found in the User
Guide and Specifications for the 24-bit module(s). For example, for sampling rates (fs) at or below 25kS/s has an input delay of 12.8/fs. For faster sampling rates, the
delay is 9.8/fs. Refer to the specifications for the valid data rates
available for the internal sample clock.
To align the signals
for analysis or display, you can shift the signal(s) by replacing the
t0 of the waveform(s) by an amount equal to the offset.
In LabVIEW, you can replace t0 of a waveform using the Get Waveform Components and Build Waveform functions. The code in Figure 1 demonstrates how you would use these functions with the NI 9233:
Figure 1
You could perform a similar operation using the input delay formula for any other module. Here is a before and after example of how your signals may look:
Figure 2
As shown in Figure 2, the subtraction of filter delay from the t0 of the DSA waveform is most helpful when plotting DSA and DAQ waveforms simultaneously. If saving the waveforms to file is most important, then removing samples is the most effective solution. For example, assume the filter delay is 12.8/fs and X is the amount of samples that occured during the filter delay. To properly align the waveforms, the first X samples need to be removed from DSA Waveform while the last X samples need to be removed from the DAQ waveform.
Please let me know if this is of help and if this works. Thanks!
11-10-2009 09:31 AM
Hi Mark,
David gives a good explanation of the general issue. Note that for the NI 9229, the module specifies a group delay of 38.4/fs + 2.6 μs, which sounds like exactly what you're seeing.
Regards,
Kyle
11-10-2009 11:25 AM
David,
Thanks for the information - I thought it might have been something to do with the ADC but your explanation has cleared up the reason behind it. As for the Get waveform components and build waveform the pictures you included didn't show up for me, could you explain a little more how you would adjust the t0 as my efforts so far have failed.
I tried to include the build waveform block, and put my data into the waveform in (to edit) and then added in an element for t0 which had the adjustment factor. However this didn't work - would I be right in saying that the signal needs to be broken down using the get waveform components and a constant added to the t0 value before rebuilding it with the build waveform block? Or am I off track here?
Thanks again for your help,
Mark
11-11-2009 10:04 AM - edited 11-11-2009 10:04 AM
Hi Mark
Many thanks for your quick reply!
Group delay is a trait inherent to delta sigma converters. All of the
NI C Series which use a delta sigma converter have a specification for
group delay in the User Manual. Group delays are typically different
for each ADC and can sometimes be different at different sampling
rates. A method to compensate for these differences in group delays is
to use a filter which delays a signal by a fractional number of
samples.
Filters are used to add delay to the module with
less delay so that the delays on both modules are the same. For
example, the NI 9215 has a group delay of 0 samples(not a delta sigma
ADC) while the NI 9229 has a group delay of 38.4 samples.... which is your 40cycle seperation. By creating
a filter with a delay length of 38.4 samples and applying it to the NI
9215 data, both modules will have the same delay and the data will be
synchronized.
Attached below are some fractional delay filters
designed using the Digital Filter Design Toolkit in LabVIEW which have
delay lengths used for some common module combinations. Please read
the readme file associated with each filter.
11-19-2009 04:26 AM - edited 11-19-2009 04:27 AM
Thanks a lot for the reply David,
Unfortunately we do not have the Digital Filter Design toolkit, and are running the base version of LabView! Meaning that we cannot implement the solution proposed without the purchase of a the toolkit at significant cost.
I have discussed it with my manager and we cannot justify purchasing the extra toolkit, so I will reside my self to post processing the data and getting it somewhere near!
Cheers again for the help!
Mark
11-19-2009 04:31 AM
Hi Mark
Many thanks for your reply. Im sorry to hear that, please feel free to contact me here at NI if you would like to discuss the toolkit further. Hope you get your application to work!