6259 multiple clocks

[gol_luiz]

Hi,

I'm a newbie on labview/daqmx/NI hardware. I have been browsing the NI forums for days but I couldn't find any similar case so far.

My hardware is USB NI-6259 and my application is to write a code to readout analog samples from a cmos image sensor. The sensor requires multiple control signals such as row and column clocks, inits and resets. In summary it works as follows: After a global reset pulse and a waiting period, the readout process starts. The readout begins with column and row reset pulses, then a sequence of N clock pulses for row selection. During each clock row pulse, there must be M column clock pulses as well. In other words I need at least 2 synchronized pulse trains with different frequencies for row and column scanning plus all resets and init pulses (1 row init pulse every N clock row pulses and 1 column init every M column clocks pulses). My questions are:

1. Is it possible to use the USB NI-6259 to generate such signals? I know there is just 2 counter inside 6259, but can I use DIO ports for those signals (timing is important)?

2. If so, can you provide some tips or examples or forums threads where I can start with?

The frequency of the clocks are to be programmed, but if I can use the 80Mz or even the 20MHz internal time reference it would be helpful

Thanks in advance for any help

Luiz

[Oli.P]

Hi Luiz,

Firstly, welcome to the Forums!

I'm Oli, an Applications Engineer for NI UK.  Synchronising pulse trains in LabVIEW is not too difficult.  As there are two counters in the 6259, that should be possible to set up.  You can use the DIO ports (probably labeled PFI) or the counter output if your specific device has one.

Can I ask you to confirm exactly which USB-6529 you have?  The part number would be useful (it should be displayed on a label attached to the device e.g.. 780114-01).  Also, can you confirm what version of LabVIEW you are using and which version of the DAQmx drivers you currently have installed.

One last question.  Have you tried to implement any code yet for your application?  I have found some examples which you might find useful too.

If you open up LabVIEW, you will find the splash screen menu has 'Find Examples...' (also available from help).  In the next screen click the 'Search' tab and type 'pulse train'.  An example called 'Gen Dig Pulse Train-Continuous' would be a good place to start.

When you are accessing each sample from the cmos sensor, will you be accessing each row in full and then progressing to the next row?

Similar to this:

>................>

<................<

>................>

etc.

It would be useful if you could provide a timing diagram so that I can see where each of your resets, inits and pulses need to be.  You can use a software defined pulse train to leave the counters free, but it depends on what frequency you will need the pulse train to run at.  It will be limited to 1kHz in software.  It is also possible to use the AO terminals to output your pulses, which might be useful.

I will have a look through some more examples and see what others might be helpful for you.

I look forward to your reply.

Kind Regards,

[gol_luiz]

Hi Oli,

Thank you for your kindness and prompt reply.

I am using a NI USB-6259 (SN 194021D-01L) with labview 10.0.1 and NO-DAQmx 9.3.5.

I have tried to use state machine implementation, but the timing is not good. I imagine that it is software-based instead of hardware-based.

I am sending the timing diagram (attached) with all signals I need to generate. For the readout step, basically the sensor has two shift registers to row and column selection. So, each init pulses will be shifted along the shift-registers to select each row/column. I also need to read a analogue signal every column clock. For my application, I would like to use the highest possible frequency for column clock or for the DAC clock.

ps.: is it possible to select the digital signal amplitude?

[Oli.P]

Hi Luiz,

Just to let you know I'm still looking into your application.  Would it be possible to send me the code you have tried so far?  It might help me to get a better grasp of what we're aiming for.

In response to your question on digital signal amplitude, the answer is no.  There are set standards for digital communication protocols which our hardware adheres to.

For example TTL logic:

Vlow = 0V to 0.8V

Vhigh = 2V to Vcc (Vcc = 5V +/- 10%)

Nearly all digital circuits use consistent logic levels.  The only way to control or change the amplitude would be to use the analogue outputs on your 6259 to output the signal, in which case you could make your own 'digital' signal.

I will post back hopefully tomorrow once I've seen the code you have tried so far and got to grips with the problem a little more.

Kind Regards,

[gol_luiz]

Hi Oli,

I'm sending what I have tried before. However I don't think it will be of any help at all. As I told you, I am a very beginner on VI programming ...

It is a state machine with 4 states (wait, reset, integrate and readout). The reset has a flat sequence structure to generate the reset pulse but, as I said, the timing is not precise. In readout, I tried to create a loop to count the numbe of pulse but it didn't work (of course).

Would be possible/easier to use signal express instead?

Regards

Luiz

[Oli.P]

Hi Luiz,

I have found a couple of examples that you might want to have a look at to get you started.  I'm not sure what the best architecture will be for this application.  Am I right in thinking that you need to have a column clock and a row clock (column operating faster) and then simply create the other pulses after a certain number of clock pulses have passed?

Do you need to generate all of the different outputs that are present in the timing diagram that you sent me?

Also, do you need to have the exposure time and readout time in your code?

What will be the number of columns, rows and 'swp' points (I'm not 100% sure what swp points are - perhaps you could explain them?)

I'll have a look into what sort of architecture will be the most appropriate.

Take a look at these examples:

Count Digital Events-Buffered-Continous-Ext-Clk.vi

Multi-Function-Ctr Pulse Train Generation for AI Sample Clock.vi

These can be found in the example finder in LabVIEW.

Kind Regards,

[gol_luiz]

Hi Oli,

I'll gave a look at those examples.

In order to make it simpler:

1. Don't worry about the DACClk (swp points). These are analogue output samples, but as I need a much higher sampling rate, I will using a waveform generator triggered by the NI equipment.

2. I would like to output csclk signal to be active just during the readout phase, but I think the system will work if it is continuous.

3. We can make csrst = rsrst and rsclk = csin 4. csrst and rsrst pulses can be generated by software because their periods are variable and big (from 1ms to 1s).

So, I was considering to make it such as:

1. Having a fast clock (80MHz if possible) as the csclk signal,

2. After M csclk periods (M=#columns=500) generate a csin pulse ("ON" period twice the csclk signal, i.e., duty cycle of 2/M)

3. After M*N csclk periods (N=#rows=400) or N csin periods generate a rsin pulse ("ON" period twice the csin signal, i.e., duty cycle of 2/N)

4. The frame period generated by a software state machine (from 1ms to 1s).

However, if I got it right, I would need 3 counters (one to generate the csclk signal and two to count it's edges and trigger csin and rsin signals) and the NI-6259 has just 2 counters. Is it right?

[Oli.P]

Hi Luiz,

Thanks for that.  I think with the complexity and number of outputs that you are going to need and also the fact that you'll need 3 counters, the only way we'll be able to do it on your hardware is by buffering the output.

I suggest that we make some code that generates an array of all the data that can then be output using a single clock.  We need two elements in the array to represent each change in state of the csclk (as that's the fastest).  Using this method, we can facilitate 'switching off' the csclk during the exposure phase too.  That will also preserve the offsets like csin and csclk.

The array would be something like:

csclkT T F F T T F F  

csinF T T F F T T F

rsclkT T T T T T T T

then each row of the array can be sent to an output.

Does that sound like it might work?

[gol_luiz]

Hi Oli,

Do you mean using the Waveform generation (DO) FIFO? In this case the maximum frequency is 10MHz, isn't it? And the FIFO has only 2048 points and we need at least 200k (500x400). Is there one fifo for each output port 0 channel? Or is it shared?

Regards

Luiz

[Oli.P]

Hi Luiz,

I wasn't referring to a FIFO.  I just meant a normal array that can be passed to the DIO ports.  A FIFO wouldn't be appropriate for this situation as you pointed out.

I meant to generate a complete array of all the data for one complete cycle of exposure and readout before outputting it to the CMOS sensor.  After we have generated the array (which would essentially be a copy of the timing diagram) we can push that out of the DIO or PFI on your device at a given clock rate.

I hope that makes more sense.

Regards,