Trouble with SIT

[Odryx]

Hello Thsa

I’m not working with your example, I’have rebuild totally every parts of your examples.

LV don’t  indicate errors but The VI in which there’s the controll the signal generation don’t work.

Attached the project that I made with the relative file VI, mdl, dll so you can find, If you want, where I have to make a mistake!

Moreover could explain me the way to set to zero all output when I stop the execution of modello_Attuatore.VI by clicking “STOP”

Thanks

Odryx

[ThSa]

If the signal generation is not working, check the Init.vi in the base rate loop.vi whether the alias names of your DAQ devices are related to simulated boards.
Additonally add indicators after the IO_Read.vi and the SIT Scheduler.vi to get information of the inport and outport values.

Please find attached the "new" base-rate-loop.vi with the additional code to reset the AO values.

ThSa




Message Edited by ThSa on 02-06-2008 05:16 PM