HW Retriggered Pulse Train With Enable Line

[JBrenem]

I've been using the "Multi-Function-Ctr Retrigg Pulse Train Generation for AI Sample Clock.vi" in the LabVIEW Example Finder to sample a waveform. It has worked very well but now I need to synchronize my acquisition with another piece of hardware. The hardware sets an "Enable" line TTL high when it is ready to acquire and I need to begin my acquisition at the next available Sync pulse. The "Enable" goes low and I need to stop acquisition after the current burst/frame is complete. I've tried using a "Pause" line and a "Digital Pattern" trigger but neither seems to work with a finite pulse train. Since it's a little diffficult to explain in text, I've attached a timing diagram.

Any suggestions? I'm using a DAQPad 6016 inLabVIEW 8.5.

[stilly32]

Thanks for the timing diagram - that makes it pretty clear. The first thing that comes to mind is to just use an external AND gate on your enable and your trigger line and use the output to retigger your finite pulse train. Another option - if the timing is relatively slow you could connect the enable line to a digital input and monitor the line. When enable goes high, start the counter and when it goes low, stop the task. The risk there is that the digital acquisition would be static (software timed) and there would be risk that you could miss a trigger if it came close enough to the rising edge.

I would go with a combination of both - use an AND gate to gate your trigger, and make sure to start the counter task beforehand so it can detect correct triggers. Use a static digital to monitor the enable line, but only use it to stop the counter task after the enable has gone high then gone back low. 

Hope this helps, please post back if this wouldn't work for you or if you have questions about these suggestions. 

Andrew S

[JBrenem]

Thanks for the suggestion! Although I was hoping to avoid adding more hardware I think my timing requirements restrict me to the "hybrid" hardware/software approach.

Here's a 1st attempt at implementation - assuming I am able to assemble the hardware is this what you had in mind? The collection will either detect a low enable line or time out to end acquisition. I'm still trying to figure out the best way to initiate acquisition. Right now it requires my external hardware set "Enable" high within 10 seconds of my application start.

Any suggestions on hardware AND gates? The DAQPad 6016 has a prototyping area built into the input terminal region. Are there any hardware AND gates I can power with the 5V out lines on the DAQPad 6016?

[stilly32 · Accepted solution]

I would handle the digital differently. If you monitor the digital in parallel and just read single points then you'll have a quick way to signal to the AI loop that the enable has gone low. I added an untested VI that should give you the idea. There's probably a better way to handle stopping both loops, I just did a quick and dirty method. Actually after looking at your VI it occurred to me that you could build up a state machine where it just looks for available samples then starts reading, and once there are no available samples after a certain period of time you would stop. You'd still need the AND gate but wouldn't need to worry about monitoring the enable line. This probably wouldn't be as quick as monitoring the enable line though.

For an AND gate, any TTL AND gate should accept a 5 V supply. If I recall right a 74LS08 should work - if you only need one you may be able to get a free sample.

cheers,

Andrew S

Message Edited by stilly32 on 01-06-2009 05:36 PM

[JBrenem]

Just to follow up on this: Thanks for the suggestion, I would up implementing a sort of timeout mechanism so I wouldn't have to explicitly monitor the Enable line. Works great, since I can set my timeout fast enough that my users don't notice any delay.

Screenshots of both the configuration and call to daqmx read attached.