How to be sure that parallel loops are executed on the same clock edge ?

[CyGa]

Hi!
I'm using parallel loops to acquire input state on a FPGA target (7811R). But how to be sure that the timed loops are executed on the same clock edge ? How to be sure that it takes the same execution time for each loop ?

[The Specialist]

Hi zy17,

It appears in your picture that each of your loops is a single cycle timed loop (SCTL).  That means (by definition) that each loop takes exactly one time cycle.  If your base loop rate is 40 MHz then each iteration must be 25 nano seconds.  If the code in the loop took longer than 25 ns it would fail to compile.  When you are not in a SCTL then you need to be concerned  how many cycles it takes to complete an operation.  As it looks in your code, you should be fine.

[CyGa]

Hi The Specialist,
Thank you for your answer. As you said, I'm sure that all code placed in the SCTL will be executed in 25ns. But I would like to know how to be sure that all SCTLs will be executed on the same clock edge. How to be sure that I enter in all Case Structures and execute the associated code on the same clock edge ??

[The Specialist]

I will almost garuntee that they do start at the same time, but I could not find the documentation to back me up.  So instead the way you could test it is like this.  Place an indicator on each loops iteration counter.  Then start the FPGA.. When you hit the abort button, if all the loops started on the same edge, all the iterations should be the same.  Does that make sense?