PCIe 6536 Sample Clock Use

[CallumJ]

Hi,

in my application I am using a PCIe 6536 to read ports from an Agilent N1231B Laser Board. As part of this I need to pulse lines low or high at a regular rate to hold data or change the axis being read. Is it possible to use a sample clock to ouput a square wave via one of the PFI channels? I could alternatively do this by writing these lines in a loop but it is preferable to do this in some method that can be set up and left running whilst other tasks are being performed.

Thanks in advance,

Callum

[Dustin_D]

Hi Callum,

Do the outputs just need to be a static frequency square wave or does the square wave need to change dynamically? If you could post some more specifications for how the interface communicates it would be helpful to answer your question.

Regards,

[CallumJ]

Hi,

so I need two static square wave outputs one at half of the frequency of the other. I have succeeded in generating one signal using the digital input sample clock. I was going to try generating the other using the output sample clock. However as all my digital lines are used for reading the data (32 bits). I have no way to generate this as it cannot be done on the PFI lines. Any help would be appreciated, I've attached a snippet of my current code.

Callum

[Dustin_D]

Hi Callum,

Here is an example from our community that will help you.  It is setup so the frequency and duty cycle are able to be changed dynamically but you can change this by enabling regeneration and writing the samples to the buffer before the loop starts.  You should be able to implement something similar running in parallel to your DI task. Good Luck!

Regards,

[CallumJ]

Hi Dustin,

that seems to be what I need. However as far as I can tell it requires a sample clock. All my DIOs are taken up reading in the data from the Agilent card. Thus I am wanting to use a PFI but you cannot use a sample clock with these. Is there any way around this? I do have another DAQ card I can use as a counter through the RTSI bus if this is going to be too difficult. It is however preferable to limit the number of cards being used.

Cheers,

Callum

[Dustin_D]

Hi Callum,

Sorry about the misunderstanding.  I overlooked the fact that all of your DIOs are all taken.  Your best option would probably to use your other DAQ to generate these output signals.

You'll only be able export your sample clock from your 6536,  You won't be able to divide it down to produce your second signal.  Sorry about the confusion earlier.  Let me know how things go!

Regards,

[CallumJ]

Hi Dustin,

I am now using the NI 6025E to output the two clocks I need to control the Agilent board. However, I am now having problems synchronising the signals. Currently I am outputting two signals. Signal one is a square wave at 10 kHz with a 95% duty cycle, when low this will update the output port on the agilent card. Signal 2 is a 10 kHz signal with 50% duty cycle, this controls the axis being read, when high it is one axis, when low another.

Now the problem is I need to be sampling at 20 kHz so as to sample once for each axis. When using the onboard clock to generate a sample clock at 20 kHzon the PCIe-6536 the clock seems to be going out of sync with the clocks on the 6025E. I am uncertain how I can synchronise these, I was trying to generate the sample clock from signal 2 but from my understanding of it you cannot generate a frequency higher than the frequency of the clock being generated fro, is this correct?

The other possibility was to use change detection to clock the reading however once again I run into the problem of not having any of the DIOs free for this. Is there some other method I could use that I am missing or would you advise me to give up this method as a lost cause. We do have a FPGA we could use to do all of this easily, however, we were hoping to avoid having to use it.

Regards,

Callum

[Dustin_D]

Callum,

It sounds you may benefit from a RTSI connection between your two boards.  This way you can share a clock for the reference clock for your output pulses and a reference for your sample clock that should keep the signals of different frequencies in phase synchronization.  Another option would be to over sample at 4 times (or more) the rate of your two other signal to be sure to catch the output from your board.

Regards, 

[CallumJ]

Hi Dustin,

I do have a RTSI cable connected but I'm not sure whether I'm going the right way about this. When I use the onboard clock of the 6536 at 20 kHz I get the picture attached (Results). What I should be getting is one channel constantly decreasing and wrapping over whilst the other stays at approximately zero. From this it seems that the clocks are moving out of phase.

To fix this I am porting the 20 MHz timebase from the 6025E to RTSI7. I then use RTSI7 as the clock source for the 6536's sample clock, as shown in the other attachment (TimebasePorting). However now I get the error saying that I am attempting to read samples that are no longer available. The requested sample was available but has since been overwritten (Error -200279). Is this a problem with specifying the rate when using an external timebase, does setting the rate work when using this? I can't think why else this error may only occur when using an external timebase when everything else remains the same.

 Regards,

Callum Johnston

[Kevin_Price]

I don't have experience with the 6536, but I *can* say that the "TimebasePorting.png" screenshot reveals at least one problem in your config.  You are expecting that by pointing to the other board's 20MHz clock and wiring in a 20 kHz sample rate, that DAQmx will figure out how to divide the clock down to perform 20 kHz sampling for you.  That isn't how those inputs get interpreted though.  DAQmx will simply "believe" that the signal you pointed at *is* itself 20 kHz.

You will need to try to use DAQmx Timing property nodes to configure a timebase divisor so you can divide 20 MHz by 1000 to get the desired 20 kHz.  By the way, I didn't realize that an E-series board could export a 20 MHz timebase across RTSI, but since you didn't seem to get a signal routing error I guess you taught me something new.

Another potential issue is that it's difficult to control the phasing of the 6025e's counters.  If you need the one counter's 5% off time to occur at a specific phase relative to the other counter's edges, it could take a little work.  The E-series counters don't support triggering, so you'd probably end up needing to make a dummy analog task just for its sample clock, and then slave the counters of the analog clock.

-Kevin P