PXI AI/AO delay?

[radioactive28]

Hi,

I'm using the PXI-6733 and PXIe-4498, and was reading about the 4498 ADC filter delays.

Is the delay a one-off thing when I start acquisition, or does it happen in every DAQmx Read cycle, such that the delay is cumulative?

Also, does the 6733 have any similar delay, and can these be disabled or corrected for somehow?

I'm asking because I noticed something that I could only explain as a phase drift, when I output a pure sine wave through the AO to a speaker, and the signal is picked up by the AI through a mic. The Read and Write VIs are residing in individual loops, each with their own task and timer.

Thanks.

[ZachHindes]

The filter delay is a constant phase delay, probaby like what you are seeing.

A good way to think about it is to consider a case where you are acquiring a signal on the PXIe-4498 simultaneously with a standard multifunction device (say an X Series).  If you're acquiring at 204.8 kS/s, the filter delay is 64 samples according to the manual.  That works about to be 312.5 microseconds.  Therefore the phase between the signal your 4498 is measuring and the signal a typical MIO is measuring would be about 312.5 microseconds.

To answer some of your other questions:

• The 6733 does not have any delay like this.
• The delay can be corrected for by throwing away some samples at the beginning of your acquisition.  If, for example, you're acquiring at 204.8 kS/s like in the example above, you should throw away the first 64 samples from the acquisition as that is old data.  In NI-DAQmx 9.2 we also added a new DAQmx channel attribute AI.RemoveFilterDelay that you can set to True to have the driver do this for you.

[radioactive28]

Thanks for the clarification, Zach.

However, the drift I was describing is actually continuous, such that even if I played 2 sine waves (one from an external stand-alone generator, one from LabView's VI) and manually adjusted them to be anti-phase, they would eventually drift to become in-phase again. Hence the question about the 6733 delay.

Any idea if this might have anything to do with phase-locking (rather, the lack of) of the Read and Write VIs, or perhaps, loop latency? I'm sampling at 10kS/s, reading and outputting 500 samples per loop iteration.

I'm actually using this as a test, within a VI that has other processing (mostly math and data logging) going on. I'd post the file, but I don't have it with me at the moment.

[radioactive28]

Hi Zach,

Back with the file examples. I've attached the application I'm using, as well as a pictorial description of the problem, the set-up for which I've described in the above post.

To explain the graph a little, the initial drop in the amplitude is when I manually adjust the phase on the hardware function generator until I get the smallest possible amplitude. From there, the phase starts to drift, and the amplitude increases as the cancellation comes undone slowly. The spike completely puzzles me, because I saw on my output graph that the phase of the sine generator VI suddenly jumped. From there, I proceeded to manually change the phase (on the hardware function gen) until the amplitude was the smallest, and the drift started again.

Do you have any idea what may be causing this? When I recorded the function generator and sine generator VI's output individually, I saw no indication of any such phase drifting.

Thanks again.

[radioactive28]

Oh, just to add: the hardware function generator and sine generator VI were both outputting their signals to different amplifiers which were driving 2 speakers. For both of these, I recorded the outputs indivdually, and neither amplitude nor phase showed any changes.