Simulating Digital I/O of FPGA on Development Computer - Strange Results... Please Help

[MichaelAtUVa]

Hello,

We have ordered a 7851R DAQ card which we haven't yet received and we are trying to simulate it using the "Development Computer" setting.  However, I can't seem to get the DIO to work correctly. In fact simply opening "Digital Line Input and Output.vi" example doesn't give the expect results. What happens in the example file is the indicators just flash constantly and are unaffected by the controls. Is this a known issue and I just need to wait for my hardware or have I done something wrong?

Thanks!

Michael 

[srm@viewpointusa.com]

This is the NI expected behavior.  Useful isn't it.  You might have been expecting to control the simulation but as I understand it, it is effectively random.  The most you can do is compile your model for the target and use conditional compilation to create your own test vector to test your code under windows.  this is wise anyway tho.

Stu

[MichaelAtUVa]

I suspected as much. Thanks Stu. Luckily our stuff is supposed to arrive shortly.

Michael

[reddog · Accepted solution]

You didn't mention which version of LabVIEW you are using, but if you're using LabVIEW 8.6, there should basically be 3 options for debugging/simulating your VI on the development computer. 

The first is to execute the VI on the development computer using random data for the FPGA I/O data.  I suspect this is the option you're currently using and may not be that useful if a lot of the logic in your VI depends on the values of the I/O data. 

The second option is to use a custom VI that supplies the simulated FPGA I/O data.  This sounds like it's what you're looking for.  When you select this option, you will also be presented with a button you can press to create a template VI that can be used to create your custom VI.  If you look at the block diagram of the template VI, I think it should be relatively straight forward to figure out how to insert your custom code. 

The third option is to execute the VI on the host computer but use real world I/O.  In this last case, a default bitfile is automatically downloaded to the FPGA for you and the data is transferred from the device by the driver.  Obviously, you can't use this last mode until your hardware actually arrives.  I hope this helps.