Simultaneous generation of phase-shifted square waves at different frequencies

[SteveP]

I need to generate from 1 to 4 square waves between 1 and 20 Hz all with the same frequency.  Each wave will be phase shifted from the previous by 1 / (Number of Outputs).  These waves are not output as individual digital bits on multiple lines.  Instead their state changes are assembled serially into a sequence then clocked out onto one digital output.  Thus this serial bit assembly will need to be generated at the digital output bit only whenever one of the individual waves has a logic state change.  Any used waves would still be included in the bit stream as logic 0.  An example for 4 phases or waves :

           Time >>> 

Wave 1 : 1 0 0 1

Wave 2 : 1 1 0 0

Wave 3 : 0 1 1 0

Wave 4 : 0 0 1 1

For 3 waves : 

           Time >>> 

Wave 1 : 1 0 0 0 1 1

Wave 2 : 1 1 1 0 0 0

Wave 3 : 0 0 1 1 1 0

Wave 4 : 0 0 0 0 0 0

I actually have 16 sets of such phase shifted waves to generate at the same time for a total of 64 individual bits to keep track of and to include in the sequential bit stream.  The 16 sets can each have a different frequency and different number of waves.  That is the part I am struggling with.  The rate at which the sequential bit stream is output (due to a change in any one bit in any set) is not constant because the different frequencies mean the time period to the next change in the any of the sets is not constant.  The overall pattern among the complete 16 sets does not repeat itself.

[Dan_K]

Hello SteveP,

I'm not sure I understand exactly what you are asking.  Are each of the waves being output on different channels of the same port, or are they being combined somehow on the same line?  What specific device are you using to implement this generation, or are you looking for some advice on which device to use?  Are you trying to generate digital signals on 16 different lines at different frequencies?

The theory of what you have explained makes sense, but I don't think there is enough information about your desired implementation.

[SteveP]

The device I am writing this digital information to accepts a clocked serial stream of 64 logic levels and has an internal latch to hold those 64 states.  So I either send it this stream when the logic state of any of the 64 changes or continuously send the stream even if its pattern had not changed.  Because the waves have different frequencies, the pattern of the 64 logic levels does not repeat.  Thus the state of the 64 levels must be continuously calculated.  Because my frequencies are low (say 20 Hz max) and the exact timing of a wave's transition is not critical, it would be sufficient to calculate the 64 levels at say a 1 msec period.  Then output that stream every 1 msec or determine if the stream pattern had changed from the previous pattern and if it did, then output it.

The 64 levels are composed of 16 sets of 4 bits.  Each set of 4 bits has the same frequency but are phase shifted from each other.  it is the calculation of the logic state at any given point in time for the 16 sets and dealing with their different  frequencies that I was looking for help with.  I am working on trying to use the Square Wave PtByPt vi to do this.

I have worked out assembling the 64 levels into the serial stream and its subsequent generation.  I am using a PCI daq card and can clock out these 64 levels in less than 1 msec using a non-M Series card. 

[Dan_K]

Hello SteveP,

How does your device take its data?  Does it take it as a series of TTL logic levels?  If so, at what rate?

It looks like all you need to do is create an array in LabVIEW to represent the data you are going to output.  Depending on the type of data your device takes this can be done in multiple ways.  One way would be to use the Square Wave VI.  Another would be the use of the VIs in your function palette under Programming»Waveform»Digital Waveform.  These VIs can be used to create a variety of digital waveforms relatively easily.