01-11-2021 10:24 AM
Hello, I am a newbie here and have a technical question.
In our system we currently use a PXIe-7841R FPGA board with 96 digital IOs and 8 analog inputs and outputs. Unfortunately the board is discontinued and we are looking for an alternative. The newer reconfigurable multifunctional IOs only have a maximum of 48 digital IOs which is too few.
One approach for a new solution would be to use the FPGA board PXIe-7821 with 128 digital IOs and to add a PXIe-6363 which provides the analog inputs.
However, the sampled analog values are processed in our FPGA logic and also the output values are generated here. The host has nothing to do with all this.
My question now is how to transfer the data between PXIe-6363 and PXIe-7821. Is it possible that the PXIe-6363 writes values to the host memory via DMA values and the PXIe-7821 reads them back without loading the host CPU with them? In the documentation I have seen so far only the case that data is moved back and forth between IO board and host.
And what would be a realistic latency for such a process? We would need a latency <2us. But is that realistic for a buffered operation?
Thanks for any help!
Marcel
01-11-2021 01:55 PM
The concept you're talking about is called "Peer-to-Peer Streaming" and unfortunately the DAQ series do not support such a feature. Any data transfer between DAQ and RIO has to be implemented on the host (CPU) application to read from DAQ and write to FIFO. The CPU will be acting as an interface between FPGA and DAQ.