cDAQ 9172 Sync

[Corentinm]

Hi,

I'm having trouble understanding the synchronization between 2 Chassis, for datalogging purposes.

My setup is the next: I have 2 cDAQ 9172 chassis, roughly 15 meters between them.

In the first cDAQ9172 (I would also like this one to be the master clock) I have 2 modules in slot 1&2: the NI9213 (reading 8 AI thermocouples)  and the NI9208 (reading 3 AI current pressure gauges).

In the second cDAQ9172 (slave clock), there is only one module, the NI9215 (reading 2 AI voltages), in slot 1.

I read a lot about the PFI lines and how to acces them, but it remains unclear to me ( I'm relatively new to labview&national instruments hardware).

http://www.ni.com/white-paper/5376/en/ 

<link no longer exists>

https://www.ni.com/docs/en-US/bundle/371747f/resource/371747f.pdf

I understand (please correct me if I'm wrong) that the PFI lines in the cDAQ9172 are only accessible on slot 5&6. I have a NI9421 DI sink and a NI9472 DO source available for routing the clock signal.
If I understand it correctly, I need to put the 9472 in the master clock chassis in slot 5or6, connect it to a power supply, and connect the DO 0/PFI0 and COM to the 9421 in slot 5or6 of the slave chassis. Is this correct?

thanks for your help!

Grtz from Belgium,

Corentin

[JosD]

Hi Corentin,

I think hat should work fine. As the 9215 on your second cDAQ does not have a delta/sigma ADC, sharing the start trigger and the sample clock should be sufficient. The first White Paper you referenced already gives some explanation on the topic. 

For the two modules on he Master chassis (9213 and 9208), the measurment will automatically be synchronized if you start them as a single task (mentioned in the webcast). A potential problem can be that different Delta Sigma modules can have a different input delay: there is an inherent input delay due to built-in analog and digital filtering. This delay can be found in the specs of your C-series modules, and it depends on you application if the difference between these delays is acceptable for you. If not, you can programmatically compensate for it.

Kind regards,

Jos Deurloo

National Instruments

Applications Engineer

[Corentinm]

OK, my synchronising setup is the following:

NI9472 in slot 6 of the Master chassis (slot 5 gave me an error ; unsupported module)

NI9421 in slot 6 of the slave chassis 

1. I connect a power supply to the NI9472 Vsup and COM. 

2. I connect the NI9472 DO0 to the NI9421 DI0 (clock signal)

3. I connect the NI9472 DO7 to the NI9421 DI7 (trigger signal)

4. I connect the NI9472 COM to the NI9421 COM

5. I program the thing in my VI as follow :

There is still no pulse coming through, what did I do wrong?

[Corentinm]

When I create a task in MAX for the NI9472, I can generate a digital line output, which the NI9421 then acquires without a problem. So that tells me they are connected allright.. Why doesnt this work with the clock and trigger routing?

extra info on my program: It runs without errors, Master chassis tasks running fine, but the task on the slave chassis doesnt run ( since it's waiting for a clock signal that isnt there I guess..)

[JosD]

Hi Corentin,

We have been in contact already concerning this issue, but I will post the solution so others might benefit from it. In the 9172 chassis, these DI/DO modules must be engaged before they can route signals to or from the timing engines. So, we configured a dummy digital task on each module to engage it before exporting the signals and starting our AI tasks. An example-vi is attached.

That means, it actually is possible to share the sample clock and trigger between the two chassis, using the 9472 and 9421.  Keep in mind that there is some lag in the output of the 9472 channel -- one tick of the 80MHz timebase -- since the output is not a direct feedthrough of the backplane signal.  For some applications, that's an acceptable amount of skew, especially for slower-sampling applications like thermocouple measurements.

I will post an example vi later.

Best regards,

Jos

[JosD]

Hi again,

The hypothesis has changed a bit -- I no longer think that there was an issue with module engagement. Instead, the 9421 seems to be able to import the signal just fine, if it comes from the 9472.

As far as the 9472 is concerned, I think we just need to make some of the documentation more clear. Based on our testing, the timing engine simply cannot drive the digital output. However, the timing signals can run a counter in the chassis, and the counters are able to drive the digital output. So the routing table needs to be updated to include a counter as a subsystem for indirect routing.

The attached VI will provide synchronization between the two chassis using via the 9472 and 9421 modules. Bear in mind that there is some lag in the 9472 output channel - 1 tick of the 80 MHz timebase - because the output is not a direct feedthrough of the backplane signal. Other hardware is required if his amount of skew is not acceptable. Possibilities: two 9401 modules for ex- and importing the sample clock, or two 9178 cDAQ chassis which have separate PFI lines on the chassis itself.

Jos