counter digital pulse gen for AI pause trigger

[caz]

I am using a pci-6132 for hardware retriggerable analog input using an external clock (LV 8.2, DAQmx 8.3).  The AI is configured for finite samples using a pause trigger to control when to sample.  The gate signal for the pause trigger is created using a counter configured for digital pulse generation using ticks of the external clock and is set retriggerable using a DAQmx property node.  The order then is,

1.) An external trigger on PFI0 starts the counter

2.) Counter puts out a pulse that is high for X ticks

3). AI samples when counter pulse is high

Attached is a picture of the signals on an external scope.  The pinkish signal is the external trigger, blue is the external sample clock, and yellow is the counter output.  In this picture, I set the AI for 2 samples and the CO to be high for 2 ticks.  My questions are these;

1)   Which 2 rising edges of the clock signal will the AI sample on and is there a way to verify this (ie. an internal signal with a rising edge for each sample)? 

       I'm guessing the middle and last since the first yellow rising edge is a little later than the blue edge.

2)   Also, will the counter always need at least 1 sample clock period after the trigger to begin digital pulse generation?

3)   How to know how many counter are being used for a task?  Is there a property for this?

Thanks

Drew

[caz]

Forgot to link

https://mywebspace.wisc.edu/awcaswell/web/NIicon/NI_timing_exclock.jpg

Drew

[Ed W]

Hi Drew,

Thank you for posting to the NI forums. 

1.  I think that your guess is correct regarding the exact signals used for the AI sampling.  However, you can test this by comparing timestamps of the analog input and the external trigger. 

2.  Depending on the internal timing of the device, it may require an extra clock period to begin digital pulse generation.  If this is an issue, you could increase the frequency of the external sample clock to remove the delay between the trigger and the pulse generation.

3.  There isn’t a property node for the number of counters being used in a task.  As a general guideline for counter tasks, if you’re performing finite pulse generation, you’ll be using two counters; if you’re performing continuous pulse generation, then you’ll only be using one counter.  Otherwise, the easiest way to determine how many counters are being used is to look at the device routes in Measurement & Automation Explorer (MAX). 

I hope this helps.  Please post back if you have any further questions.

Ed W.

Applications Engineer

National Instruments

[caz]

Thank you for the reply Ed W.  For comparing timestamps as you mentioned in 1), I am a little unsure how the driver correlates the timing between the 2 different tasks I have configured.  For instance, with a waveform read on the AI, will the start time be when the task was started or when the pause trigger signal goes high.  Also, how do I get a timestamp for the external trigger?

Also, regarding 2), it shouldn't be an issue and unfortunately the sample clock can't increase in frequency.  For achieving  multiple hardware triggered acquisitions on S series boards, I normally configure a retriggerable counter for digital pulse train generation and use this signal for the sample clock.  However, in this case, the sample clock I need is this external signal and I don't think I can use this signal for counter digital pulse generation at the same frequency.  The only way to do something similar is to use the external clock as the sample clock and also the source of ticks for a single digital pulse generation which is then used as the pause trigger for the AI.

I've added the code and attached the picture from my first post since the webhosting will not work after a while

Thanks

Drew

[Ed W]

Hi,

One easy way to correlate the digital signal with each analog sample is to simply add another analog channel to your AI task.  Then jumper the clocking signal to this extra analog input channel, and view the results in a single waveform.  From this, you will be able to test exactly which rising edge the analog input is using with only minimal modifications to your existing code.

Ed W.

Applications Engineer

National Instruments