09-13-2006 11:25 AM
09-15-2006 05:42 AM
Hi,
Unlike other National Instruments data acquisition families, the 6110/11 family of data acquisition boards uses a pipelined analog-to-digital converter (ADC). In a pipelined ADC, each sample passes into a three-point analog first-in-first-out (FIFO) buffer before being sent to PC memory over the PCI bus. The rising edge of the scan clock signal digitizes a sample and it is sent into the next stage of the FIFO with the next clock signal, which begins the conversion of the second sample. The sample must pass through three different stages of the FIFO, and therefore, is not flushed across the PCI bus until three additional scan clock edges occur.
As the data is passed from stage to stage, it is stored on capacitors. If the time between sequential scan clock pulses is too long, the data in a particular stage will be lost. Therefore, there is a maximum time in which data can be stored in a stage. This is what sets the minimum sampling rate for the device.
http://forums.ni.com/ni/board/message?board.id=250&message.id=8122&requireLogin=False
http://digital.ni.com/public.nsf/websearch/80AD7297BB958D1286256B690004EAA4?OpenDocument
That means an external scan clock will not reduce the sample rate any further - what are you needing to acheive? Simultaneous sampling on x channels at what frequency? (other hardware may be more appropriate - the 6120 has no minimum sample rate) or you could average the higher rate sampling to give yourself the reduced data set and factor out some of the noise you might have acquired with your signal.
Hope that helps
Sacha Emery
National Instruments (UK)
09-15-2006 05:48 AM