Connect digital analog ground

[pcurt]

Greetings.

I have a mixed-signal Multisim design which I have forward annotated to Ultiboard.  My Multisim circuits use 2 different grounds - net 0 and net DGND.  For simplicity, I would like to prototype a first version of the boards with the grounds logically connected, so I don't need to worry about ground loops being created by the fact that I'm using separate digital and analog lab supplies.

I have checked the box in Multisim under "Sheet Properties -> PCB -> Connect digital ground to analog ground."  I have transferred my design to Ultiboard 11 and specified a 4 layer board.  Layer 3 is my ground plane, with a large copper area connected to Net 0.  While placing components and vias on my board, I'm noticing that the thru-holes and vias I define as connected to Net 0 appear as I expect - with the "+" thermal relief on layer 3.  However, vias logically connected to DGND are appearing on layer 3 with large areas of copper removed (I've specified 12 mils clearance on each copper layer).  If I change the copper area on layer 3 to net DGND, instead of net 0, I notice the reverse situation.  All of my analog ground vias and thru-holes have copper cleared away, and the DGND vias are now filled.

I don't believe a logical connection exists between net 0 and DGND in the forward annotated netlist.  Is there some way I can confirm this?  Did I miss a step in the process while trying to connect these two?

[Mark J]

Hi there,

The way it works when you select "merge analog and digital ground" in Multisim is that all nets that are either "0" or "GND" will get resolved to net "0" upon export. By the time you get over to Ultiboard, it only knows about a net called "0". So if you create a power plane connected to net 0, then all pins that were connected to net 0 OR net "GND" in Multisim should have the "+" thermal reliefs. Incidentally, when you are ready to split these nets aparts, if you uncheck "merge analog and digital ground" and forward-annotate, you should see the creation of a "GND" net and the appropriate updates to the netlist in Ultiboard.

I'm guessing that the confusion lies in with what we call "DGND". In our POWER_SOURCES family, we have a "DGND" (that incidentally has a label of "GND" when placed down). This is our digital ground but it actually resolves to the net name "GND" if "connect analog and digital ground" is left unchecked.

Is there a Multisim sample file you can provide that outlines the scenario where you are getting pins connected to a net called "DGND"?

Mark

[pcurt]

Thank you for your reply, Mark.

I was going to upload my Multisim project file, but then realized a lot of my components are now in my Corporate Database, so I can keep vendor and manufacturer-specific part numberings and inventory quantities all together in the same place.  Instead, I took some screenshots and created a .pdf file.  I uploaded the pdf file to transferbigfiles.com, here.

First, I snipped some sections of my design to illustrate the current state of things.  On the first page, you can see that my default sheet properties are setup such that digital and analog grounds should be connected.  I have an FMC-LPC connector "J17" in my design, with the "DGND" wired to it.  The J17B pin actually represents about 40 different SMD pads on a VITA 57 connector.  The DGND component is from the Master Database under Power Sources, though I think I renamed it from "DGND" to "GND."  As you can see, Ultiboard is showing a lot of DRC errors right now because the vias are set to assume net "0" while the SMD pads were exported as connected to net DGND.

Next page, I unchecked the box "Connect digital ground to analog ground" and forward annotated the changes.  Ultiboard found no differences.

Next I thought that perhaps my renaming of the default Refdes from "GND" to "DGND" could be the problem.  So I went through my design and replaced all of my "DGND" triangles with the DGND component from the Master Database.  As you pointed out, though the component is named "DGND" the Refdes is actually "GND."  I left the sheet properties as is, with digital /analog grounds not connected.  When I forward annotate the changes, I observe what I expect - the DGND connections are removed and replaced with GND connections.  (Next page) The SMD pads are now logically connected to the net named GND instead of DGND.

Finally, I went back to Multisim and tried combining the nets "GND" and "0" automatically by selecting the check box in Sheet Properties.  Unfortunately, when I forward annotate, Ultiboard detects no changes.

Following are 2 relevant sections of my .ewnet file I opened in a text editor, after my latest changes.

	(net "0"
		(trackwidth "6.00000000e+000")
		(trackwidth_max "3.93700787e+002")
		(trackwidth_min "6.00000000e+000")
		(clearance_to_trace "6.00000000e+000")
		(clearance_to_pad "6.00000000e+000")
		(clearance_to_via "6.00000000e+000")
		(clearance_to_copper "6.00000000e+000")
		(routing_layer "1111")
		(net_GUID "{8704ACB4-9808-4086-9C22-02206D379B13}")
	)

	(net "GND"
		(net_GUID "{8EFCFB7F-F038-4362-A59D-667354159F44}")
	)

Message Edited by pcurt on 02-22-2010 10:48 AM

[pcurt]

I'm not sure what I did, but it appears to be working now.  Net "GND" in my schematic is now being export as net "0" in the .ewnet file.

Thank you for your help.

[pcurt]

And now I am trying to forward annotate a change to Ultiboard, and it is attempting to switch all of the net "0" connections back to net "GND."  I didn't even touch that particular section of my schematic, nor did I open the Sheet properties window.

[Mark J]

Thanks for putting together the *.pdf file.

The fact that when you forward-annotate, net "GND" is being re-added means that it exists in the *.ewnet export from Multisim. Can you verify that this is the case and the "merge analog and digital ground" is still checked? One thing to mention is that there is a checkbox on this page called "Save As Default" (which is by default checked). This saves these PCB settings, including number of layers, and the merge option, as defaults for the next design you open. Another question is whether or not you are working with hierarchical blocks, and if so, are you doing any editing to these sheet properties outside of the top-sheet?

Just wondering if, with all the troubleshooting, the "merge analog and digital" got accidentally unchecked, leaving "GND" in the *.ewnet file and causing annotation to want to create this net in Ultiboard?

Barring that, I recommend creating a support request at ni.com/ask. Getting some sample files/components and a simple reproduce is probably that quickest way we can get to the bottom of this.

Thanks,

Mark

[pcurt]

I have been using hierarchical blocks in my design.  I also have been using the "Save as Default" check box as well.

Mentioning the hierarchical blocks gave me an idea:  I swithced up my top-level sheet and opened "Sheet Properties."  Under the PCB section, the "Connect digital ground to analog ground" was checked.  I unchecked it, clicked apply, then re-checked it.  I just forward annotated and it worked! My exported netlist contains no GND, only a net 0.

Now if refocus my window to the hierarchical block I was working in, and try to forward annotate, the netlist now contains both nets GND and 0.  I cancel the forward annotation.  Go back to the top-level sheet and forward annotate.  No differences are detected.

It seems that forward annotation works as long as the current sheet in focus in Multisim is the top-level sheet.  If one of my hierarchical blocks are focused, the annotation does NOT merge nets 0 and GND.

[Mark J]

Yep, I've been able to reproduce this behaviour and will enter it as a defect. For the time being, I recommend  always clicking on the top-level sheet when performing an annotation to ensure that the PCB settings are being obeyed.

Thanks for following up with us on the troubleshooting you did with this hierarchical block scenario.

Regards,

Mark

[dbur]

I just went through the process of learning this as well.

I did discover an additional thing.  If I connect a DGND and AGND symbol together in MS it works.  It gives a warning that they canot be connected together, but allows it anyway.  The FA then merges ground correctly regardless of which page is up when you do it.