11-29-2007 06:58 AM
Any help will be readily accepted!
Robin.
11-29-2007 08:10 AM - edited 11-29-2007 08:11 AM
11-29-2007 09:12 AM
11-29-2007 09:40 AM
11-29-2007 10:02 AM
11-29-2007 05:19 PM
11-29-2007 05:30 PM
11-29-2007 09:00 PM
I don't like to jump onto someone else's thread, but since we are discussing DRC errors and thier causes I have a question.
I was exporting a simple circuit from Multisim to troubleshoot a question on the forum. What I did was have 2 resistors in series and then have this in parallel with another 2 in series. I then exported this to Ultiboard and autoplaced them. The result was 3 resistors R1-R3 stacked one above the other with R4 directly across from them. The DRC flag came up and said that the 3 stacked resistors were too close and almost overlapping. My autoplace component spacing was set to 20 mill, so why wasn't that used to separate these components? Why did it ignore this setting?
If this is a known issue please let me know
11-29-2007 09:51 PM
11-30-2007 08:08 AM