Different trace width with respect to the others nets

[irocz]

Hello, I have the following problem that is very crucial for most of the proffesional users.

Let supposd that design consists of three lines "nets". The first one exhibits 10V potential, second and third one exhibits 1000V and 1010V, respectively.

So it is clear that a trace clerance between net 1) and 2) shloud be much highier than beteween 2) and 3). The voltage difference between 1) and 2) is equal to 990 V while the same value for the net 2) and 3) is eqaul only to 10V. How can I fix this different clearnace values into MultiSim/Utlibord design software. I was thinking that by creating net group one can fix trace clerance property within the same net that is ofcourse different from those nets that are not grouped.

I am looking forward to hearing from you

Best regards

Pawel

[irocz]

Hello, I have solved this problem. It is my fall. These option works fine in Multisim !!!!!

But I have the next problem that follows the main topic presented above. How to fix different trace width for the same net. Namely, one can has a net that is separated into two separate tracks. Then the current that go throught these nets is different and smaller than the original one according to the fundamental law Iout = Iin1 + Iin2, but the net name is still the same in MULTISIM. How to fix this problem ?????????.  

[GarretF]

Hi irocz,

If I understand your question, this is not possible in Multisim. Wires in Multisim indicate which items are connected, but they do not represent trace segments on the physical PCB. You can specify some net PCB information in Multisim, but that information only applies to the net as a whole, not individual pieces of copper, because Multisim doesn't know how you will layout the net.

In Ultiboard, you can set the trace width per trace. Just double click the trace, and set the trace width on the General tab.

[irocz · Accepted solution]

Thank you very much for your support. That's very important for me .

Best Reagrds

Irocz