Getting a double clocking error w/at least ls273 and 164

[Euler's_Identity]

I designed a rather elaborate and time consuming circuit.  I simulated it with the "real" as opposed to the "ideal" digital simulation setting.  With the "ideal" setting, I get no glitch.   With the "real" setting I get a glitch.

The glitch seems to relate to fast rises.

The 74ls273 only looks at the clock's level not its rise time.  But, just the same, I even tried a 74ls14  Schmitt trigger.   It still would not lose the glitch.

My original design was the 74ls273, but, just to be sure, I went to a dedicated shift register as opposed to my wired one from the octal D package.  I still got the clock glitch.

Next I set everything up quick and dirty fashion in another schematic, created just to solve this mystery glitch problem.

I forced, via a spst switch, only a clock rise while a high was on deck.  Yep, the friggin' thing set both Qa and Qb!

Go to the "ideal"simulation setting (which won't give you realistic TTL levels), and the clock only fires once, a textbook clean fast rise.  But go to "real" in the digital simulation settings, and the clock rises past three volts twice.  Therefore, even though the glitch is on the order of about 500 psecs total, you get two clock rises and, thus, an erroneous mystery shift.  Or, if you use the 74ls273, the Q output gets this mystery glitch.  ...which doesn't make sense, as leaving D high, Q should never set, clear, and then set, even if there is a dirty clock. ;-|


I've spent many hours chasing this thing down.  It's just this simple:

1.  Set your digital simulation setting to "real"
2.  Drop in 74ls273, clear it, and setup D0=high
3.  Produce a low to high transition at the clock input
4.  View Q0
5.  Try to figure out why Q0 goes high, drops low, and then goes high again
6.  Give up after various circuit tweaks and try a 74ls164
7.  Try to figure out why both Qa and Qb go high with a single low to high transition of the clock
8.  Try to figure out why it seems that in "real" setting you get an unreal double hit of rising edges

Any ideas? 


       

 

[Euler's_Identity]

Here's the 164-based simple circuit which demonstrates the mystery clock glitch. 

Yes, I also did a transient analysis on the off-hand chance that it was a scope problem.  No, Multisim is taking a single rising edge command and making it a double rising edge and, from the best I know, entirely of its own accord. 

You betcha.  I'm not a happy camper.  I'm still hoping it's my error in some way, because I need clean clocks and "real" simulations.

[Euler's_Identity]

Here's the 74ls273 version of the glitch.

[Euler's_Identity]

I just tried the 74ls164 IC version.  No joy.

How in the heck can I make a non dirty real clock?!

[lacy]

I didn't exactly see everything you described, but I did see that on the probes it was lighting 2 everytime the clock signal transitioned. This indicated to me that it was being triggered twice for each positive transition of the clock and the clock signal actually shows this as indicated by your scope reading and what I saw also. Q0 didn't seem to rise and fall as you described or I just didin't see that.

What could be causing this? I suspect it is the inverter in the clock circuit. I removed this and rewired the switch into the circuit to produce the same thing that the inverter was trying to accomplish and the circuit seemed to work correctly. I do not know why this inverter is causing a problem, but it is intoducing unwanted oscillations.

I will repost the circuit for you to look at with my modification. If you have to use the inverter then I do not know what to tell you because I tried various ways of hooking it up and still had more or less the same results.

Here it is:

[Euler's_Identity]

It didn't work.  (The clock is dirty.)

Perhaps it's something in my settings?  ...it works for you, right?

[Euler's_Identity]

My circuit needs this (or the other) chip driven by a gate.

I just tried it with a standard 74ls04 inverter.  Nope.

Yes, it does seem to like a simple switch, but even then not really, as I still get a glitch.  Perhaps when the switch is used they're assuming there was bounce and automatically cancel it, thus cancelling the error also?  ...but it remains in the clock's waveform...

With my circuit it is imperitive that I drive a ring counter with a gated clock and that I do not get a double clock hit.

True, I could just go ahead and build, assuming it's Multisim's error, but... !

[Euler's_Identity]

Just to see what would happen, I added another ls inverter and changed the switch.  This way the switch would not bounce, because I was opening it.

It still doesn't work.

Something is up with a fast rising clock, but it gets ignored if the clock pin driven is looking into a switch and not an ls gate's output.

[lacy]

I tried something else here. I noticed that on the last circuit you posted you had a resistor tied from ground to the clock line in addition to the one tied back to VCC. This would be R4 in the origianl schematic. I also noticed that in this circuit I saw no double tripping of the clock signal but it did have a sloping rising edge. I am assuming this is what you are refering to as being dirty. Not a clean square wave by any means.

I removed this extra resistor from the clock line and re-added the inverter and this seemed to clean up this slope. I do, not know what  purpose you may have had for this resistor but I believe that to be causing the sloping edge. I was incorrect about the inverter. I just know that in the original configuration I didin't get the double clocking when it was removed, but I failed to notice the sloping of the edge of the signal. Now with this new information I hope this will get it the way you want it.

I will repost the circuit with my modifications. Let me know what you think. Just so you will know I am using asll default settings with the exception of the digital setting which is set to REAL.

Here it is:

[Euler's_Identity]

I've been playing with that last circuit some more.  I notice that I don't get a double hit taking the switch to open and leaving it there, but I do if I bring it back.

I noted the tell-tale glitch on the leading edge when monitoring between the two inverters.  This leads more substance to the hypothesis that it's about fast rising edges, because now the fast rising edge is between the inverters.  However, since it's between the inverters, of course it gets passed through to the clock input of the shift register and, then, both Qa and Qb get set. 😞

So, I conclude this is about Multisim 10/10.1, and I'm still hoping it's a setting that's wrong.