How do I merge nets in Ultiboard 10

[Mike Howes]

I have a mixture of components in a circuit. The ground net is labelled as net 0, a TTL component connected to it has its ground pin labelled as GND and a CMOS component has its ground pin labelled as VSS. What I want to do is merge the GND and VSS nets to the 0 net.

[nestor-sg]

Hi Mike, the correct way to do it is throught the use of Net Bridges. You will find them in Place > Net Bridge. Select a net bridge from the database ( you can create your own if you do not like those ) arrange each side of the bridge to be tied to one of the nets you want to "connect" (not merge) and place it so that each side touches each trace.

Doing it this way, will still keep those nets as separate nets, but it will connect them and will not give you any DRC error.

[kittmaster]

I've found this out the hard way and hundreds of dollar later, but here is the way it works in my opinion.....I've never been a fan of net bridges (no offense) because the pyramid design method requires that all nets be generated by the schematic capture and not down the pyramid while you "hope and pray" you connected it via a bridge not defined in the top of the pyramid. When/if you go back in say 4 years for an update.....you going to remember the net bridge.........mostly likely not! Don't be a victim of your own design, it's best to have a 100% generated netlist that doesn't need any modification later on....ESPECIALLY if you port the design to another package.....like.......PADS, ORCAD.....you see?

So the fix that will keep true compatibility and fix your issue here is this......place the TTL component (Multisim), double click on it, click the "pins" tab.....you'll see 5 cells with each name of pins and functions......click on the VCC "cell" UNDER THE NET COLUMN >>>>>> type whatever the EXACT name of the net you want it "merged" too. Do this for ground......BINGO..........DONE......no worry about bridging it downstream in the design.......and the pyramid design is complete and no error can/will ever occur......and your netlist will be 100%

Enjoy.

Message Edited by kittmaster on 05-17-2008 11:25 PM

[lacy]

That is a real good technique, Chris. I do have one question. After you change the net designation, will it simulate in Multisim after doing this or is this a change that needs to be made after doing the simulation before you shove it off to Ultiboard?

Thanks for the information.

[kittmaster]

I've yet to see it fail on a simulation. Since the SPICE engine takes into account all of the reference nodes and connections, a TTL offset error could occur if a "noisey" analog supply is acting up or a fault is entered.

Since TTL is inherently noisy anyway, most likely you'd begin to see artifacts in small single analog circuits with the TTL and the net 0 combined in this fashion......which in reality, is real world analysis due to the fact this is how it would be wired in hardware and controlled by proper layout.

So the short answer.....no issues to date.

Chris

[Mike Howes]

Thanks Kitmaster, that worked a treat.