MS/UB 12.0.1: Where does clearance enforcement start?

[Who_Knew]

I just transfered a design from MS to UB and received DRC errors  such as net x too close to net y, and so forth. 

The Nets list in UB spreadsheet view showed a variety of clearances set.  Some were zero, others were larger than the clearance value I had set up in the board design rules before transfering.  This makes me think something MS must be driving these values.

When I go back to MS and look at the spreadsheet view for components, I only see part spacing.  The spreadsheet view for nets shows a great deal of possible settings, but they're all blank.

Where do these clearance values come from?  Does MS inheret them from the footprints of the parts selected during the schematic entry?

Is there a design rules data entry dialog in MS that would let me drive these values ? 

It seems pointless to set up design rules for a PCB in UB, then transfer a schematic design over to UB and have the transfered data override the PCB design rules.  That demotes design rules to being just settings.  I'm thinking when I work with design rules, I'm describing all of the restrictions regarding how I want the PCB to turn out from UB, including restrictions required for the PCB to turn out correctly from the fab house, regardless of the data that comes from the schematic entry.  A design rule cannot afford to be so flexible as to be changed by a source other than me manipulating the design rule from a design rules dialog.  A DRC error should indicate at some point that the imported netlist's values are not in agreement with the PCB design rules, or some such.

Thanks

[Miguel_V · Accepted solution]

Hello,

Well I might not be fully understanding your question, but I'll try to answer what I think you are asking. All the clearance settings that you can add in Multisim (the ones in the spreadsheet viewer) have a default setting in Ultiboard usually being the allowed maximum or the default size (So a max trace width by default will be the largest size available in Ultiboard, while a min will be the shortest possible - within constraints, a width will be the default size - 10 mils). If these fields are filled up in Multisim, then they should override the Ultiboard defaults when transferring your design. As for component clearances, these cannot be set in Multisim, only in Ultiboard (in the component properties), however, you can define all clearances for nets.

As for transferring and annotation, when you forward or backward annotate to and from, The pop up dialog that asks you if the changes are ok will notify you of any change in clearances so you can ignore them all or assign the changes to specific nets.

Kind Regards,