Nets not connected when they should be

[david_c_partridge]

You may recall that not long ago I had some problems with the simulation of the 74HC163.   One of them turned out to be because Vcc wasn't connected to one of the pins even though the schematic capture in MS showed that it was.

I've now had a similar problem which resulted in two 74HC74's having their Set and Clear pins connected together but not connected to Vcc as they should have been.   The schematic capture in MS showed they were connected.

This one got all the way through to real PCBs .

Luckily a couple of short EC wires between pins 1 and 14  solved the problem.

It's only when I turned on display of all net names (normally I only display net names on selected nets), that I could see that the connections between set and clear were not on the Vcc net.   Zooming in as far as you like to the connection between Vcc and this net just showed a normal junction and to all intents and purposes it looked to be connected.

I get the impression that there's some sort of a bug here (though of course I can't reproduce it consistently - and believe me I've tried to come up with a scenario that will consistently create the problem).

Yes, I could have checked the netlist in detail (not a job for the faint hearted, and nigh on impossible for any large project) or spotted it when routing the PCB, but it's too darn easy to miss this sort of problem - when you're routing nets, you don't always think about what that net does, you just concentrate on how best to lay down the copper.  And if you didn't design the circuit yourself, the chances of spotting it go down to amost nil .

It may (or may not) be relevant that this project was started using EWB 10.0.1

Cheers

Dave

[lacy]

I hate to hear that this is still causing a problem and that the error propogated to the actual board. I am curious as to whether, since you stated that you started the project in 10.0.1, that something occured when loading it into 10.1. I know this is something that NI is going to have to investigate, but I thought I would pass along my thoughts.

It would look like to me that the ERC would flag it in the situatuon you describe here. Maybe next time, just to see if it will, try running an ERC check inside Multisim and see what happens. This is all I can tell you do try as, like you say, it is very dificult if not impossible to try and re-create.

I really hope that NI can help you get this straightened out somehow.

[david_c_partridge]

I'd run ERC checks - so they didn't catch it.    Whether the problem was there in 10.0.1 and just carried through to 10.1 or happened as the project was opened for the first time in 10.1 I really don't know.

Dave

[sahpe]

Hello David,

I have been looking at your issue and also read your previous post. These seem to be the same problem and I believe the best way forward is for me to escalate this problem to our R&D department.

If this is consistent with other similar components then we really need to investigate this further. Have you seen this behaviour with any other parts? I would like to hear about it if you have.

Once there is an update as to how we are going to go about fixing this I will make sure I get back to you and let you know what was done.

I hope this is not causing you more issues at the moment and that I will have an update for you soon,  

Kind Regards,

Michael S.
Applications Engineer
NI UK & Ireland

[david_c_partridge]

I've not see it with other parts, but suspect (though cannot prove) that this is a problem with connecting two nets together, rather than being part specific.

In this case I drew the conection from set to clear and then dropped a Vcc source on the schematic and either moved the Vcc source up to the net so it automatically connected to it, or placed a junction and drew the connection (I fear I don't remember which of these I did, though I *think* it was the latter).

HTH Dave