Phase lock loop design

[musicholic]

I downloaded Phase lock loop ms file that somebody posted in 2006.

I want to it to run at high frequency, 13Mhz to 15Mhz.

I set VCO frequency rage from 13 to 15Mhz at 0V to 5V.

Input signal is 14Mhz, and I want to this PLL to lock at 14Mhz.

However, I cannot design loop filter.

Anybody can help me?

[supsup]

On a picture filter calculation is shown:

[musicholic]

I tiried that, but it doesn't work.

Any suggestion?

[supsup]

Series 40ХХ will not work on such frequency. To you it is necessary either to reduce frequency, or to use more high-frequency series IC.

[musicholic]

According to the datasheet, the typical frequency is 1.3Mhz at VCC = 10V.

So, I think that the circuit should work on that frequency.

[supsup]

At series  40хх at U=10V time of transition for other logic level can reach 100ns. Therefore the phase detector even on frequency 1,3 MHz, most likely, will correctly not work. And on frequency 13 MHz it is better to use a series 74HC.