TTL Digital Clock - Wire output feeding 2 active low inputs (LOAD, CLR) only activates one of the inputs when LOW

[Zmeu]

I'm designing a digital 12 hour clock using TTL. I'm using decade counters to increment the time for the seconds, minutes, and hours. My problem is for the hours:

The hours of a normal clock usually reset when hitting 12 back to 1. The logic for this is easy, since I'm using 2 decade counters for the 10's and 1's of the hour, I NAND whenever the 10's output is 1 and the 1's output is 3. The output of this NAND goes into the active low RESET of the 10's and the active low LOAD of the 1's (because I want to load hour 1, there is no 0 hour). My problem is that only the CLR gets activated during that short LOW pulse, and the 1's stays at the current value of 3.

I've been troubleshooting this for the last hour and I can't figure it out... Any help is greatly appreciated.

PS. My circuit allows for presetting the clock. The switch hotkeys are 'a' and 'space'. To increment the hours when simulating, press 'a' twice, and 'space' twice to increment. Also be aware that the clock LED displays are backwards, so the hours start from the right, 10's of hours, 1's of hours, 10's of minutes, 1's of minutes, etc...

Message Edited by Zmeu on 04-06-2010 11:23 PM

Message Edited by Zmeu on 04-06-2010 11:23 PM

[Zmeu]

Figured it out, the decade counters I was using have synchronous LOAD and asynchronous CLR. CLR would clear right away while LOAD would wait for the next clock pulse and the condition would no longer be true.

[yyao]

Haha, what an adventure eh? In a way, I am sad (and nostalgic) for discrete logic components. But then again, some days, I am not.

[Dwayne]

Zmeu,

Thanks for posting your circuit!  It helped solve a problem on my own decade counting circuit in lab