12-09-2008 10:14 AM
12-09-2008 11:52 AM - edited 12-09-2008 11:55 AM
Hi,
The way you have it connected is correct. Are you loading the output of the with a large load?
See attached pictures.
12-09-2008 12:06 PM
12-09-2008 12:12 PM
12-09-2008 01:09 PM
Hi,
It looks like that by default, Multisim's voltmeter has very low input resistance compared to the multimeter. The default input resistance for a voltmeter is 10MOhm while the default input resistance of a Multimeter is 10GOhm. So, if you want to use a voltmeter, you'll have to increase its internal resistance:
1 - Double click the voltmeter
2 - Open the Value tab
3 - Change the unit of Resistance from MOhm to GOhm
4 - Click OK
It seems that Multisim has a very pessimistic view about logic gate drive strengths and most gates can only drive very high impedance loads.
Also, if you want to attach images in this forum, just click on Add Attachments when you submit a post or a reply.
12-09-2008 02:29 PM
12-09-2008 04:58 PM - edited 12-09-2008 04:58 PM
Actually, I think this behaviour is actually the result of a bug. We have fixed this problem and this will be corrected in our next release.
In the meantime, I can make a suggestion for a work around if you are able to modify your circuit. You can connect multiple open collector gates (such as the 74LS05) to 1 resistor connected to VCC (see attached picture and schematic). Open collector gates can output a low signal (i.e. sink current), but are unable to output a high signal (i.e. source current). Like tristate buffers, their outputs can be connected together. The node labeled Out acts as the shared party line and any of the 4 (or how ever many you desire) gates can pull the party line low. If no gates (U1 to U4) are pulling low, then the output node stays high. If you design your logic right, only one gate should be switching between low and high while all the others should be dormant (i.e. outputing "high" ) at any given time.
This design is very similar to using tristate buffers except for the inversion in the output signal. It is a safer design than using buffers since it is impossible for different gates to be competing against each other. The disadvantages are in the higher power dissipation and longer rising delays.
Hopefully, that helps. Unfortunately we won't be able to release the patch for this defect right now, but it is secheduled to be released for our 10.1.1 update.
07-25-2010 11:13 PM
Hello, Yi!
Do you mean that all buffers have that bug? And is it possible to fix it in MS 10.1 or I'll have to buy the next MS? I have the same problem with tristate buffers:
http://forums.ni.com/t5/Circuit-Design-Suite-Multisim/I-really-need-help-with-8051/td-p/1170915