shift register PISO model

[sean_surge]

Hi, I'm trying to build a parellel in-serial out shift register, had no luck with this so far. Basically, stores the input bits (from the word generator) in to the D flip flops. Then shift the bits to the right by changing the write/shift bit to 1.

If someone can help me with this would be great

[sean_surge]

the output is totally wrong and not what expected and is random. I assumed it was something to do with the frequencies of the storing and shifting bits and needed to be synchronised. but no luck so far  

[sean_surge]

schematic -- http://en.wikipedia.org/wiki/File:4-Bit_PISO_Shift_Register.png