subcircuits much slower than hierarchical blocks?

[aamailhot]

Forgive me for not having a specific issue here, but this is the situation I am in:

I have a circuit made up of ~60 smaller portions of several different types, which I have naturally made into their own components. The choice between subcircuits/HB's seemed simple enough: i wasn't going to be implimenting the components often outside of this circuit so I therefore made them SC's so that I may have a single all-in-one file for easy transportation (to my manager, ect.).

Suffice it to say, I have been struggling the last week with my circuit full of sc's to make the simplest changes. The delays between actions are quite astounding, some of note include:

~5 sec for a paste command, regardless of the size of what is being pasted

~5 sec to move an entity, regardless of the size of what is being moved (considerably faster when associated nets don't have to be remapped)

~10 sec to connect nets (seems to take the longest time to connect nets of SC's, because of the pin name conflict perhaps?)

Compare this to a near-identical circuit that I was required to make, which I opted to impliment with HB's this time in order to experiment. I find that performing any of the above actions causes delays at most on the scale of miliseconds, perhaps faster.

How can these values be true? My intuition tells me that both sc's and hb's should increase the delays, but if anything an HB scenario should have greater delays as they have to access external files. Is it because the WHOLE circuit is getting recursively updated when an action is performed in the SC scenario? This strikes me as unnecessary if it is so.

I will learn to utilize HB's if that is the solution, though I find it tedious to reset the path destinations of the HB files if I were to say, move the whole directory to my manager's computer. Is there perhaps a way to set a relative path to all files within a circuit? Something like '<main directory>/HBs'?

Thanks and sorry for the rather lengthy ambiguous post.

Also, I unfortunately cannot include the designs as they are proprietary, though I am sure I could put together some example circuits that exibit the same behavior if it'll help with investigating this issue.

-aamailhot 

[dbur]

I've had the same problems, only I wait many minutes rather than seconds. 

I've avoided HB's since having problems with multisection symbols and netliost errors in past designs.  If it is faster that might be a strong reason to push for those problems to be fixed and start using HB's again.

I read this thread and wrote this whole message in less time than it took to change one refdes.

[nestor-sg]

aamailhot:

We have run benchmarks with the use of SCs vs. HBs with no significant differences in performance. It would really help if we can test your files to check exactly where this performance hit is originating. We might be missing something in our tests or there might be other reasons for this problem.

Could you send me a private message through the forums with the email address that NI has in file so that our support team generates an outbound email to which you can reply with files. If you'd rather have me send you the private message let me know.

Also, please include info on the exact version of Multisim being used... is it 11.0.2? (Help > About Multisim).

Cheers,