HDL Interface Node 的Code-->"architecture implementation of halnode is" 和 "begin" 這兩個是xilinx fft ip 經過compile之產生一個vhd的檔我是照 裡面檔案格式放的 不是有個有architecture和begin的副程式之下，分別放入，還有library也要建立，ip的接腳也要建立
例如：
entity fft is
port (
fwd_inv_we : in STD_LOGIC := 'X';
rfd : out STD_LOGIC;
start : in STD_LOGIC := 'X';
fwd_inv : in STD_LOGIC := 'X';
dv : out STD_LOGIC;
scale_sch_we : in STD_LOGIC := 'X';
done : out STD_LOGIC;
clk : in STD_LOGIC := 'X';
busy : out STD_LOGIC;
edone : out STD_LOGIC;
scale_sch : in STD_LOGIC_VECTOR ( 9 downto 0 );
xn_re : in STD_LOGIC_VECTOR ( 15 downto 0 );
xk_im : out STD_LOGIC_VECTOR ( 15 downto 0 );
xn_index : out STD_LOGIC_VECTOR ( 9 downto 0 );
xk_re : out STD_LOGIC_VECTOR ( 15 downto 0 );
xn_im : in STD_LOGIC_VECTOR ( 15 downto 0 );
xk_index : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end fft;
architecture STRUCTURE of fft is
signal sig00000001 : STD_LOGIC;
signal sig00000002 : STD_LOGIC;
signal sig00000003 : STD_LOGIC;
signal sig00000004 : STD_LOGIC;
signal sig00000005 : STD_LOGIC;
signal sig00000006 : STD_LOGIC;
signal sig00000007 : STD_LOGIC;
signal sig00000008 : STD_LOGIC;
signal sig00000009 : STD_LOGIC;
signal sig0000000a : STD_LOGIC;
signal sig0000000b : STD_LOGIC;
signal sig0000000c : STD_LOGIC;
......
begin
sig0000005f <= scale_sch(9);
sig00000060 <= scale_sch(8);
sig00000061 <= scale_sch(7);
sig00000062 <= scale_sch(6);
sig00000063 <= scale_sch(5);
sig00000064 <= scale_sch(4);
sig00000065 <= scale_sch(3);
sig00000066 <= scale_sch(2);
sig00000067 <= scale_sch(1);
sig00000068 <= scale_sch(0);
sig0000003c <= xn_re(15);
sig0000003d <= xn_re(14);
sig0000003e <= xn_re(13);
sig0000003f <= xn_re(12);
sig00000040 <= xn_re(11);
sig00000041 <= xn_re(10);
sig00000042 <= xn_re(9);
sig00000043 <= xn_re(8);
sig00000044 <= xn_re(7);
sig00000045 <= xn_re(6);
sig00000046 <= xn_re(5);
sig00000047 <= xn_re(4);
sig00000048 <= xn_re(3);
sig00000049 <= xn_re(2);
sig0000004a <= xn_re(1);
sig0000004b <= xn_re(0);
