IRQ使用方法?

[Compact RIO]

想請教NI工程師: 

我使用CompactRIO 9014 

IRQ是同步化的連結器，

在FPGA的IRQ中，

IRQ Number是想與RT作同步化的數值輸入?(同步想傳到RT)

Wait Until Cleared是指?

最後輸出端 ERROR?

但我看HELP看不太懂，不知有FPGA與RT作同步化連結範例可以參考或解說嗎。

另外有個同步化的小問題，因為FPGA執行速度較快，RT較慢，

如果在FPGA中設Loop Timer設 1uSec

RT設1kSec，那如果使用IRQ會如何?

此外我為了想FPGA與RT同步化，在FPGA設置100HZ的取樣頻率(Loop Timer)，並在RT使用Timed Loop，回圈執行時間為100HZ，

但總覺得沒同步化，還是上面我的觀念設法錯誤。

                                                                                      謝謝

[iluvcali]

IRQ Number specifies which logical interrupt to assert. The default is 0.

There can be several IRQs you want to use. So the number specifies different IRQs. Typical supported values are 0 through 31.

Wait Until Cleared specifies if this VI waits until the host VI acknowledges the logical interrupt or this VI asserts the interrupt and continues. Set this parameter to TRUE if you want the VI to wait until the host VI acknowledges it. Set this parameter to FALSE if you do not want the VI to wait. The default is FALSE.

Once the IRQ is executed in an FPGA VI, Wait on IRQ in an RT VI will get the permission to continue the following codes. But in the mean while the codes in the FPGA VI will keep going. If you want the FPGA to iterate after the RT VI finishes its behavior, you would have to set Wait Until Cleared true.

Error indicates whether an error has occurred. Currently, there are no error conditions for the Interrupt VI, and this output always returns FALSE. 

So it will always be false. Nothing has to do with it.

Here is some info that might be helpful:

Reference Example for Streaming Data from FPGA to cRIO to Windows

What is the Best Method For Synchronizing a LabVIEW FPGA and a Host Interface VI?