This post is part of a series on what's new in Circuit Design Suite 12.0
Version 12.0 includes a new DRC check for overlapping vias. (Ultiboard always had a check if copper objects were too close such as vias were to close, but there is now an additional check specific for vias that will detect if the vias are connected.) Now, if two vias are within the via-to-via clearance and are drilled such that they go through at least one common layer, Ultiboard will highlight this condition as a DRC error.
As before, if you don't want to see this class of errors, you can hide the error using the Filter Manager by right-clicking in the DRC tab and selecting Filter Manager.
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