Engine Simulation Custom Device Feedback

[StephenB]

I do not know why you have never encountered this problem before, but your PXI system is incorrectly configured. As you can see, it says PXI (Unidentified) with a yellow exclamation mark. You must right click and identify the controller, and then right click and identify the chassis. Otherwise you will be unable to use multiple PXI single-point devices simultaneously because NI VeriStand cannot route sample clocks between them. it is a quick thing to do though, couple of right cliks

[StephenB]

jamesy wrote:

I don't have an "identify as" option I have an "rename alias" option. should I give my alias a name? RIO0 ?  james

Right click the PXI chassis. Not the RIO device

[jamesy]

Stevie,  I think that just solved everything. I just added your PXI-7854R VR Example.lvbitx bitfile and now the cycle and crank angles are incrementing 🙂  One thing, what .fpgaconfig file should I use for your example ?   PXI-7854R Engine Sim Hall FPGA Example.fpgaconfig throws an error but it runs ok without one.   james.

[jamesy]

Hi Steven,  I made lots of progress today after this issue was resolved. I modified my VI to add an RIO analog input. I then modified my .fpgaconfig file to reflect these new RIOs. I also changed the names of some Fuel injector and ignition coil variables.  I deployed and everything looked great for about 5 minutes.  Suddenly I noticed crank and cam were no longer being transmitted. ( on the scope ) The engine and cycle angles are incrementing ok. I checked and the error code status channel == 61003.  Any ideas? I looked online and I see it may be linked to my .fpgaconfig changes. I was sure to increment the number of packets in the file by 2.  I also am not getting this error attached when I open my sysdef, maybe its related.   I've re-booted my chassis, real time PC and local PC several times, same issue.  James

[StephenB]

jamesy wrote:

Stevie,  I think that just solved everything. I just added your PXI-7854R VR Example.lvbitx bitfile and now the cycle and crank angles are incrementing   One thing, what .fpgaconfig file should I use for your example ?   PXI-7854R Engine Sim Hall FPGA Example.fpgaconfig throws an error but it runs ok without one.   james.

Hi James,

I just tested this and it works for me. Remember that Engine Simulation FPGA IP is separate and different than single-point IO IP. The only example bitfile provided that combines both single-point IO and engine sim IP is "PXI-7854R Hall Example with Single Point IO.lvbitx" So this bitfile can be loaded by the 'FPGA' section via an fpgaconfig file and by the Engine Simulation Custom Device.

To load it, just make sure these files are all in the same directory, when you select the fpgaconfig from NI VeriStand's 'FPGA' section:

• PXI-7854R Hall Example with Single Point IO.lvbitx
• PXI-7854R Engine Sim Hall FPGA Example.fpgaconfig
• NI VeriStand FPGA DMA.xsd (located in <Public Documents>\National Instruments\NI VeriStand <year>\FPGA)

[StephenB]

jamesy wrote:

Hi Steven,  I made lots of progress today after this issue was resolved. I modified my VI to add an RIO analog input. I then modified my .fpgaconfig file to reflect these new RIOs. I also changed the names of some Fuel injector and ignition coil variables.  I deployed and everything looked great for about 5 minutes.  Suddenly I noticed crank and cam were no longer being transmitted. ( on the scope ) The engine and cycle angles are incrementing ok. I checked and the error code status channel == 61003.  Any ideas? I looked online and I see it may be linked to my .fpgaconfig changes. I was sure to increment the number of packets in the file by 2.  I also am not getting this error attached when I open my sysdef, maybe its related.   I've re-booted my chassis, real time PC and local PC several times, same issue.  James

That code (61003) is actually a warning (since it is not negative), and is OK and can be ignored. It just means multiple things are accessing the FPGA, which is expected. Your code and XML look fine.

The lack of output from the FPGA is strange. Does the output ever work? As in, does it work after deploy and then stop working some time later? Clearly, the FPGA is running as you are seeing the angles increase.

The error screenshot you posted is an error if you try to open multiple instances of NI VeriStand on your host computer and is not related. Perhaps you should restart your host computer?

[jamesy]

Hi Steven,  This was my mistake, loose connection. The error code threw me off and I assumed it was a veristand issue. Now everything works great. Thank you for your excellent excellent support!! I have a deadline to meet tomorrow and have been making major changes to the labview code. Hopefully everything will go smoothly today and tomorrow.  James.

[StephenB]

James,

I'm so happy to hear this! Thanks for following up. Glad it worked with your deadline

[jamesy]

Hi Steve , I am on the home stretch but have run into a problem with my DIO channels.  These seemed to be working fine until I made a change to the DMA read packets and fpgaconfig file.  I added Connector 0 digital inputs to the Read and modified my fpgaconfig file.  I have 5 packets.  I reviewed the fpgaconfig file several times and it looks fine.   When I use a pule generator to stimulate the DIOs sometimes the wrong channel toggles. for example DI24 connector 1 is actually DI 25. I've added my VI and fpga config .  James

[StephenB]

Hi James,

I dont see anything wrong. Since this is a general NI VeriStand question and not specific to engine simulation, you should call up NI and open a support request.