Engine Simulation Custom Device Feedback

[StephenB]

A next-generation engine simulation toolkit is available at: NI Engine Simulation Toolkit for NI VeriStand. The new toolkit offers vast improvements to FPGA space utilization, RT performance, and many new features.

[jamesy]

Hi Steven,  We have been using the old engine simulation device for over a year and it works great. We may upgrade soon to your new version. I have a small feature that I need to implement.  When I get a rising edge on any ign pulse, drive an output high on the fpga 200 crank degrees later for about 20ms. Is there some easy way I can do this? I know there a lot of labview restrictions when working in labview on an FPGA. any pointers would be great.  thanks, James.

[StephenB]

Hi Jamesy,

Glad to hear that!

To answer your question, the new Engine Simulation Toolkit FPGA IP includes a 'common' library of helpful code that is leveraged throughout all the actual engine IP. In here, there are several things you could use to accomplish your task. I know this is the new library, but you can look at how these were implemented to do the same thing in the old library. Or upgrade.

I threw an example together real quick that uses a state machine that should probably work. Obviously I havent tested this though.

[jamesy]

Great stuff,     I'll have a look at these kind of blocks in the labview help and see if i can use this king of setup. I also found a link which looks promising: http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/customizing_i_o/   I have the full AES Engine simulation running with many FPGA loops reading fuel injector angles etc and a comms loop. The cranks and cam are generated too by veristand.   My approach in the past when adding new features was to re-build the entire model and see if my changes worked.  The one hour build time really sucks so debugging is a nightmare.  I know there is a way to run the entire thing locally without building it. Any pointers?  I'm thinking a way to increment engine angle from the labview front panel my self and set the actuator inputs to 1/0 myself manually.   Then i could really speed up debugging of new features. I'm guessing this would mean modifying and then un-modifying my model when switching to debug or full build mode?  regards, Jamesy

[jamesy]

oh in addition to above, I'm using labview/veristand 2012 for now. Can i still see the "common" vi's when i install it?  Will the install corrupt my current 2012 old engine simulation tool kit ?  I'd plan just to look at the VIs and then re-create them in 2012 old engine sim setup.  James

[StephenB]

Hey Jamesy,

The custom device relies on some technology that only is present in 2013 and later, so the LabVIEW code is actually saved in LV 2013. So you will have to find a computer with that to take a look.

Yes you can install them side by side. I actually have them both installed.

For your general FPGA questions I suggest working with our product support team. They will be the best resource.

[jamesy]

Ok I think we have some 2013's around.  I'll ask those guys about the FPGA debug mode thanks again, James

[jamesy]

Hi Steven , I'm having an issue using the crank setup in the custom device.  When I set the crank cycle setting to "cycle angle 720" and enter a "location of missing teeth after TDC" greater than 360, there is no missing teeth transmitted by the FPGA. I checked on a scope.  I want to set my "location of missing teeth after TDC" to 624 degrees cycle angle.   To resolve this: can I simply use the "crank angle" setting and use 624/2 = 312 ?   Will this cause any issues as my cam settings are set using engine cycle and my crank would be set using cycle angle?  Also, if I enter the location of TDC using a 0-360 scale, how does Veristand know where to put the TDC? there will now be 2 occurrences every 720 of the point I specified.   The easiest way is to fix the 720 somehow in my current custom device, do you have you any clues?   Plan B is to install the latest version of the custom device. I already did this and rebuild my code but didn't see any of the nice new data replay functionality. I'm guessing I have to update my labview libraries with some files and then rebuild the code.

[StephenB]

Hi Jamesy,

Can you provide some additional information so I can best assist you?

• What version of NI VeriStand are you using?
• What version of the Engine Simulation Custom Device are you using?
• What version of the AES library are you using?
• Can you provide your system definition file, configured to show the issue?
• Can you provide your LabVIEW FPGA code, configured to show the issue?

There may be some confusion on the intended use of the 'cycle/crank angle' setting. Or there may be a bug.

Take care,

[jamesy]

Hi Stephen,   to resolve this issue , I made the jump forward on Friday to the latest Engine SIM custom device. 3.10  I then loaded the latest AES 2.7 library. veristand 2012  I went ahead and added FPGA code for the crank playback , I've included the VI.  I plan on using crank logs to playback the signal from the vehicle.  The build passed ok.  I then tried to load the bitfile in veristand, I got the error " "Invalid bitfile." image and bit file attached.