Engine Simulation Custom Device Feedback

[jamesy]

also added the VI

[jamesy]

I've been using "LabVIEW FPGA Advanced Interface Tools_2010+ (1).zip" all along

[jamesy]

Note  made a copy of the original VI and called it  HIL2_Engine_Sim_EA888 I added it to the original project and removed the old one. Is there something I have forgotten to do with the .fgpaconfig file ?  The original one is still residing in my project.  I notice you provide an example file. note also your pre-compiled bitfile loads fine into veristand "PXI-7854R VR Example.lvbitx"

[StephenB]

Looks like the problem is you're APU has a control named "APU.Degrees per Tick 2" it should be "APU.Degrees per Tick"

Looking at your FPGA code, I should note that you no longer need 4 APUs with the new code engine sim toolkit code (since you can cylinder offset your event measurements easily now). Whenever you have time to migrate it should be pretty nice

[jamesy]

Hey Steven,  Nice , that was it, I re-built and the custom device now loads into veristand ok. I see 2 new problems,  1. When I input the engine speed in the veristand screen using   ......engine simulation/Angle processing unit / engine speed  the crank angle and cycle angle do not increment, they stay at 0.  I looked at the new angle processing VI and I notice you have some new acceleration settings, something called APU.Increment Rate . Do I have to set this to some number before building my labview FPGA code?  I left it at the default. I can't see any other reason why my crank and cycle would not be incrementing.  2. when I input a csv into veristand for the crank analog output everything looks fine until I press "confirm selection" then my graph disappears. I've now way of knowing if veristand really accepted the crank data until I resolve point 1. above.   thanks, James

[jamesy]

Hi Steven,  To debug 1. above I loaded your prebuilt bitfile : PXI-7854R VR Example.lvbitx added your .csv file : crank VR data.csv in veristand. Still when I save the veristand project the crank graph disappears. ( not sure if it really loads )  deployed it.  set the engine speed to > 0. Problem : still my crank and engine angles stay at 0.  I then went to you VI (VR Example.vi) and rebuilt it for my project, allocating my FPGA I/O Deployed it, same issue.  Have I missed a setting in veristand/labview?  thanks, James.

[StephenB]

Hi Jamesy,

Glad it loads now

In the Engine Sim custom device, the display of the CSV data is only done when you press the refresh graph button. The idea was to avoid loading a possibly very large file and therefore slow down the GUI. So if it looks OK after you press the refresh graph button... then it will load that way. If you want to see the graph again, select refresh graph again. In the Engine Simulation Toolkit Custom Device, the graph now refreshes automatically.

For your question about engine angle staying at zero: Yes there is a new acceleration setting, but by default he acceleration is Inf so it doesn't do anything. You can verify this by visiting the angle processing unit page in the system explorer. Setting the APU.Increment Rate default value inside the FPGA code does nothing as the custom device will overwrite this value before it starts the code. The crank/cycle angle may be staying at zero if the custom device is throwing an error.

1. Can you check the value in the Status Channels/Error Code channel?
2. If there is a non zero value there, can you connect to the web interface of your target with a web browser, go to the console page, and copy and paste the error here?

[jamesy]

Hi Stevie,  I don't see an error when I run your code. just the crank and cycle angles stat at 0. Status Channels/Error Code == 0  I then went ahead and rebuilt my original code ( which has been working for 1 year) I tried to load it and got this weird Error attached, and it would not deploy.  I rebooted by computer and re-installed the custom device. same error.  This and getting worse here 😞  I added a screen shot of the console from the web browser as it would not let me copy it.  James

[StephenB]

Hi Jamesy,

That error occurs because you are trying to load different bitfiles to the same RIO#. Make sure that if you're using the same FPGA from multiple places in NI VeriStand that you are using the same bitfile. In your case I think that is in the hardware->chassis->fpga section (the file referenced from your .fpgaconfig) and from the engine simulation custom device.

I don't know why the APU wouldn't rotate with your new code. Can you provide me your files and I will try to reproduce?

• sysdef
• labview project
• bitfile
• tell me what hardware you're using

[jamesy]

Hi Stevie,  Can you explain, "trying to load different bitfiles " ?  One change I made this time, I kept multiple copies of VIs in my project and then only selected the "TOP Level VI" when I did a build. I then specified the location of the built bitfile depending on which VI I was building.  let me send you my project.  thanks,, James